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| HIGH-VOLTAGE MIXED-SIGNAL IC 80 x 104RGB C-STN LCD Controller-Driver w/ 32-shade per dot, 12-bit per RGB (Dither 221K) ES Specifications Revision 0.6 August 11, 2003 ULTRACHIP The Coolest LCD Driver. Ever!! UC1682 80x104RGB CSTN Controller-Driver TABLE OF CONTENT INTRODUCTION ................................................................................................................ 1 MAIN APPLICATIONS ....................................................................................................... 1 FEATURE HIGHLIGHTS.................................................................................................... 1 ORDERING INFORMATION .............................................................................................. 2 BLOCK DIAGRAM ............................................................................................................. 4 PIN DESCRIPTION ............................................................................................................ 5 REFERENCE COG LAYOUT ............................................................................................ 9 COMMAND TABLE.......................................................................................................... 13 COMMAND DESCRIPTION ............................................................................................. 15 LCD VOLTAGE SETTING ............................................................................................... 29 VLCD QUICK REFERENCE............................................................................................... 30 LCD DISPLAY CONTROLS............................................................................................. 32 HOST INTERFACE .......................................................................................................... 35 DISPLAY DATA RAM ...................................................................................................... 42 RESET & POWER MANAGEMENT ................................................................................ 45 ABSOLUTE MAXIMUM RATINGS .................................................................................. 49 SPECIFICATIONS............................................................................................................ 50 AC CHARACTERISTICS ................................................................................................. 51 PHYSICAL DIMENSIONS................................................................................................ 58 ALIGNMENT MARK INFORMATION.............................................................................. 59 PI INFORMATION ............................................................................................................ 60 PAD COORDINATES....................................................................................................... 61 TRAY INFORMATION...................................................................................................... 65 COF INFORMATION ........................................................................................................ 66 REVISION HISTORY........................................................................................................ 68 Revision 0.6 1 UC1682 80x104RGB CSTN Controller-Driver UC1682 Single-Chip, Ultra-Low Power 80COM x 312SEG Matrix Passive Color LCD Controller-Driver * Support industry standard 3-wire, 4-wire serial bus (S9, S8, S8uc) and 8-bit/4-bit parallel bus (8080 or 6800). Special driver structure and gray shade modulation scheme. Ultra-low power consumption under all display patterns. Fully programmable Mux Rate, partial display window, Bias Ratio and Line Rate allow many flexible power management options. Software programmable frame rates up to 250Hz. Support the use of fast Liquid Crystal material for speedy LCD response. Software programmable four temperature compensation coefficients. On-chip Power-ON Reset and Software Reset command, make RST pin optional. Self-configuring 10x charge pump with onchip pumping capacitors. Only 2/3 external capacitors are required to operate. Flexible data addressing/mapping schemes to support wide ranges of software models and LCD layout placements. Very low pin count (9~10 pins with S9) allows exceptional image quality in COG format on conventional ITO glass. Many on-chip and I/O pad layout features to support optimized COG applications. VDD (digital) range: 1.8V ~ 3.3V VDD (analog) range: 2.4V ~ 3.3V 5.0V ~ 10.5V LCD VOP range: Available OTP VLCD trimming option to support precise LCD contrast matching Available in COF and gold bump dies Bump pitch: 41.5M Bump gap: 17M Bump surface: 3,000M2 INTRODUCTION UC1682 is an advanced high-voltage mixedsignal CMOS IC, especially designed for the display needs of ultra-low power hand-held devices. This chip employs UltraChip's unique DCC (Direct Capacitor Coupling) driver architecture to achieve near crosstalk free images, with well balanced gray shades and vivid colors. In addition to low power COM and SEG drivers, UC1682 contains all necessary circuits for high-V LCD power supply, bias voltage generation, timing generation and graphics data memory. Advanced circuit design techniques are employed to minimize external component counts and reduce connector size while achieving extremely low power consumption. * * * * * * MAIN APPLICATIONS * Cellular Phones and other battery operated palm top devices or portable Instruments * FEATURE HIGHLIGHTS * Single chip controller-driver for 80x104 matrix C-STN LCD with comprehensive support for input format and color depth: 8-bit RGB: 256 color 12-bit RGB: 4K color 16-bit RGB: 56K color (dithering) 24-bit RGB: 221K color (dithering) One software readable ID pin to support configurable vender identification. Partial scroll function and programmable data update window to support flexible manipulation of screen data. Support both row ordered and column ordered display buffer RAM access. * * * * * * * * Revision 0.6 1 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 ORDERING INFORMATION Part Number UC1682xHCZ UC1682tHCZ UC1682xFBZ UC1682tFBZ Convention note: Grayed-out contents are functions not available yet. Versions Gold Bumped Die with PI Gold Bumped Die with PI COF COF Description Without OTP option With OTP option Without OTP option with OTP option 2 ES Specifications UC1682 80x104RGB CSTN Controller-Driver General Notes APPLICATION INFORMATION For improved readability, the specification contains many application data points. When application information is given, it is advisory and does not form part of the specification for the device. BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of UltraChip's delivery. There is no post waffle saw/pack testing performed on individual die. Although the latest processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, UltraChip has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, it is the responsibility of the customer to test and qualify their applications in which the die is to be used. UltraChip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. OTP CELL LIGHT SENSITIVITY The OTP memory cell is sensitive to photon excitation. Under extended exposure to strong ambient light, the OTP cells can lose its content before the specified memory retention time span. The system designer is advised to provide proper light shields to realize full OTP content retention performance. LIFE SUPPORT APPLICATIONS These devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to result in personal injuries. Customer using or selling these products for use in such applications do so at their own risk. Revision 0.6 3 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 BLOCK DIAGRAM PAGE ADDRESS GENERATOR ROW ADDRESS GENERATOR DATA RAM I/O BUFFER POWER-ON & RESET CONTROL COLUMN ADDRESS GENERATOR LEVEL SHIFTER CLOCK & TIMING GEN. DISPLAY DATA RAM CONTROL & STATUS REGISTER DISPLAY DATA LATCHES COMMAND HOST INTERFACE LEVEL SHIFTERS SEG DRIVERS VLCD & BIAS GENERATOR CL CB0 CB1 4 COM DRIVERS ES Specifications UC1682 80x104RGB CSTN Controller-Driver PIN DESCRIPTION Name Type Pins MAIN POWER SUPPLY VDD2/VDD3 is the analog power supply and it should be connected to the same power source. VDD is the digital power supply and it should be connected to a voltage source that is no higher than VDD2/VDD3. Please maintain the following relationship: VDD+1V VDD2/3 VDD. Description VDD VDD2 VDD3 PWR "Minimize the trace resistance for VDD and VDD2/VDD3. VSS VSS2 GND Ground. Connect VSS and VSS2 to the shared GND pin. Minimize the trace resistance for this node. LCD POWER SUPPLY & VOLTAGE CONTROL This is the reference voltage to generate the actual SEG driving voltage. VBIAS can be used to fine tune VLCD by external variable resistors. Internal resistor network has been provided to simplify external trimming circuit. The following network is sufficient for most applications. 330K VDD2/ VDD3 VBIAS VBIAS I 1M/VR An internal RC filter is provided to filter noise on the VBIAS pin. When not used, it is OK to leave VBIAS open circuit. If noise starts to cause problem, connect a small bypass capacitor between VBIAS and VSS. In the OTP version, this pin is disconnected from internal circuit. So, there is no need to add bypass capacitor for this pin for OTP version. LCD Bias Voltages. These are the voltage sources to provide SEG driving currents. These voltages are generated internally. Connect capacitors of CBX value between VBX+ and VBX-. The resistance of these traces directly affects the driving strength of SEG electrodes and impacts the image of the LCD module. Minimize the trace resistance is critical in achieving high quality image. Wire to corresponding VB1/2x pin. Merge ITO traces between corresponding SBx and VBx in COG. High voltage LCD Power Supply. Connect these pins together. PWR By-pass capacitor CL is optional. It can be connected between VLCD and VSS. When CL is used, keep the trace resistance under 300 . VB1+ VB1- VB0+ VB0- PWR SB1+ SB1- SB0+ SB0- VLCD-IN VLCD-OUT I NOTE * Recommended capacitor values: CB: 150~250x LCD load capacitance or 2.2F (2V), whichever is higher. CL: (Optional) 5nF~50nF (16V) is appropriate for most applications. Revision 0.6 5 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 Description HOST INTERFACE Bus mode: The interface bus mode is determined by BM[1:0] and D[7:6] by the following relationship: BM[1:0] 11 10 D[7:6] Data Data 0X 0X 10 10 11 Mode 6800/8-bit 8080/8-bit 6800/4-bit 8080/4-bit 3-wire SPI w/ 9-bit token (S9: conventional) 4-wire SPI w/ 8-bit token (S8: conventional) 3/4-wire SPI w/ 8-bit token (S8uc: Ultra-Compact) Name Type Pins BM0 BM1 I 01 00 01 00 00 CS1 CS0 I 2 Chip Select. Chip is selected when CS1="H" and CS0 = "L". When the chip is not selected, D[7:0] will be high impedance. When RST="L", all control registers are re-initialized by their default states. Since UC1682 has built-in Power-ON Reset and Software Reset command, RST pin is not required for proper chip operation. An RC Filter has been included on-chip. There is no need for external RC noise filter. When RST is not used, connect the pin to VDD. RST I CD I Select Control data or Display data for read/write operation. In S9 modes, CD pin is not used. Connect CD to VSS when not used. "L": Control data "H": Display data ID pin is for production control. The connection will affect the content of D[7] when using Get Status command. Connect to VDD for "H" or VSS for "L". WR[1:0] controls the read/write operation of the host interface. See Host Interface section for more detail. ID I WR0 WR1 I In parallel mode, WR[1:0] meaning depends on whether the interface is in the 6800 mode or the 8080 mode. In serial interface modes, these two pins are not used, connect them to VSS. Bi-directional bus for both serial and parallel host interfaces. In serial modes, connect D[0] to SCK, D[3] to SDA, BM=0x BM=1x (Parallel) (Parallel) D0/D4 D0 D0 D1/D5 D1 D1 D2/D6 D2 D2 D3/D7 D3 D3 - D4 D4 - D5 D5 - D6 D6 0 D7 D7 Connect unused pins to VSS. BM=01 (S9) SCK - - SDA - - 0 1 BM=00 (S8/S8uc) SCK - - SDA - - S8/S8uc 1 D0~D7 I/O 6 ES Specifications UC1682 80x104RGB CSTN Controller-Driver Name SEG1 ~ SEG312 COM1 ~ COM80 Type Pins Description HIGH VOLTAGE LCD DRIVER OUTPUT SEG (column) driver outputs. Support up to 104 x RGB pixels. Leave unused drivers open-circuit. COM (row) driver outputs. Support up to 80 rows. Leave unused COM drivers open-circuit. HV HV When designing LCM, always start from COM1. If the LCM has N pixel rows and N is less than 80, set CEN to be N-1, and leave COM drivers [N+1 ~ 80] open-circuit. MISC. PINS Auxiliary VDD. These pins are connected to the main VDD bus on chip. They are provided to facilitate chip configurations in COG and COF applications. These pins should not be used to provide VDD power to the chip. It is not necessary to connect VDDX to main VDD externally. Test control. This pin has on-chip pull-up/down resistor. Leave it open during normal operation. VDDX O TST4 I/HV TST4 is also used as one of the high voltage programming power supply for OTP operation. For COG design with OTP options, please wire out TST4 with an ITO trace resistance of 200 or less. Test I/O pins. Leave these pins open during normal use. Test control. Leave these pins open during normal use. TST2 TP[5:1] I/O I Note: Several control registers will specify "0 based index" for COM and SEG electrodes. In those situations, COMX or SEGX will correspond to index X-1, and the value ranges for those index registers will be 0~79 for COM and 0~311 for SEG. Revision 0.6 7 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 RECOMMENDED COG LAYOUT Users can use either OTP control (through TST4 pin) or external circuit (through VBIAS pin) to fine tune VLCD. Please refer to the following figures: FIGURE 1: Example for TST4 COG layout when using OTP control to fine tune VLCD FIGURE 2: Example for VBIAS COG layout when using external circuit to fine tune VLCD 8 ES Specifications UC1682 80x104RGB CSTN Controller-Driver REFERENCE COG LAYOUT FPC BONDING AREA COM_pad<46> COM_pad<48> dummy2 COM_pad<24> COM_pad<26> COM_pad<28> COM_pad<2> COM_pad<4> dummy1 NC D7 D6 D5 D4 D3 D2 D1 D0 RST CS0 CD WR0 WR1 TST4 VSS ~ VSS2 VSS ~ VSS2 VSS ~ VSS2 VSS ~ VSS2 VSS ~ VSS2 VDD ~ VDD3 VDD ~ VDD3 VDD ~ VDD3 VDD ~ VDD3 VDD ~ VDD3 VB0+ ~ SB0+ VB0+ ~ SB0+ VB0+ ~ SB0+ VB1+ ~ SB1+ VB1+ ~ SB1+ VB1+ ~ SB1+ VB1- ~ SB1VB1- ~ SB1VB1- ~ SB1VB1- ~ SB1VB0- ~ SB0VB0- ~ SB0VB0- ~ SB0VB0- ~ SB0VLCD VLCD NC COM_pad<50> COM_pad<52> SEG_pad<312> SEG_pad<311> COM_pad<78> COM_pad<80> D7 VDDX D6 D5 D4 D3 D2 D1 D0 VREF RST_ CS1 VDDX CS0 CD WR0 VDDX WR1 BM0 VDDX BM1 TST4 TST4 TST3 TST2 TST1 PRG3 PRG2 PRG1 ID VSS VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VDD3 VDD3 VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 SEG_pad<196> SEG_pad<195> SEG_pad<194> VDD VDD VDD VDD VDD VDD VB0P VB0P VB0P VB0P VB0P VB0P VB0P VB0P VB0P VB0P_S VB1P VB1P VB1P VB1P VB1P VB1P VB1P VB1P VB1P VB1P_S VB1N VB1N VB1N VB1N VB1N VB1N VB1N VB1N VB1N VB1N_S SEG_pad<62> SEG_pad<61> SEG_pad<60> SEG_pad<59> VB0N VB0N VB0N VB0N VB0N VB0N VB0N VB0N VB0N VB0N_S VLCDIN VLCDIN VLCDOUT VLCDOUT COM_pad<79> COM_pad<77> COM_pad<51> COM_pad<49> SEG_pad<2> SEG_pad<1> Notes for VDD with COG: The VDD=1.8V-typ operation condition of UC1682 should be met under all LCM formats. Unless VDD, VDD2/3 ITO trances can each be controlled to be 5 or lower, otherwise VDD-VDD2/3 separation can cause the actual on-chip VDD to drop below VDD=1.7V during high speed data write condition. Therefore, for COG, VDD-VDD2/3 separation is not suitable for pure ITO based COG designs. Revision 0.6 9 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 CONTROL REGISTERS UC1682 contains registers which control the chip operation. These registers can be modified by commands. The following table is a summary of the control registers, their meanings and their default values. Commands supported by UC1682 will be described in the next two sections. First, a summary table, followed by a detailed instruction-by-instruction description. Name: Default: Name SL The Symbolic reference of the register. Note that, some symbol name refers to bits (flags) within another register. Numbers shown in Bold font are default values after Power-Up-Reset and System-Reset. Bits 7 Default 0H Description Scroll Line. Scroll the displayed image up by SL rows. The valid SL value is between 0 (for no scrolling) and (79- 2xFL). Setting SL outside of this range causes undefined effect on the displayed image. Fixed Lines. The first FLx2 lines of each frame are fixed and are not affected by scrolling (SL). When FL is non-zero, the screen is effectively separated into two regions: one scrollable, one non-scrollable. When partial display mode is activated, the display of these 2xFL lines is also controlled by LC[0]. CR CA RA BR 7 7 7 2 0H 0H 0H 3H Return Column Address. Useful for cursor implementation. Display Data RAM Column Address (counted in RGB triplet) (Used in Host to Display Data RAM access) Display Data RAM Row Address (Used in Host to Display Data RAM access) Bias Ratio. The ratio between VLCD and VBIAS. 00b: 5 01b: 7 10b: 8 11b: 9 Temperature Compensation (per oC) 01b: -0.10% 00b: -0.05% 10b: -0.15% 11b: -0.20% Electronic Potentiometer to fine tune VBIAS and VLCD PM offset. The effective PM value PMV = PM+PMO-32. Make sure PMV formula does not overflow or underflow. (Available only on OTP version). Operating Modes (Read only) 10b: Sleep 11b: Normal 01b: (Not used) 00b: Reset Access the connected status of ID pin. R/G/B Write Data mask bits MSK[2:0] = {MR, MG, MB} (Default: 000b) 0: Write 1: Block Reset in progress. Host Interface not ready DH Power Control. PC[1:0]: 00b: LCD: 9nF 10b: LCD: 12~16nF PC[3:2]: 00b: External VLCD 01b: LCD: 9~12nF 11b: LCD: 16~22nF 11b: Internal VLCD (Standard) FL 4 0H TC 2 0H PM PMO OM 8 6 2 55H 20H - ID MSK RS PC 1 3 1 4 PIN 0H 10 ES Specifications UC1682 80x104RGB CSTN Controller-Driver Name DC Bits 5 Default 18H Description Display Control: DC[0]: PXV: Pixels Inverse. Bit-wise data inversion. (Default 0: OFF) DC[1]: APO: All Pixels ON (Default 0: OFF) DC[2]: Display ON/OFF (Default 0: OFF) DC[3]: Gray-shade Modulation mode. 0: 8-shade mode 1: 32-shade Mode DC[4]: Dither Function Control. 0: Disable Dither Function 1: Enable Dither Function Address Control: AC[0]: WA: Automatic column/row Wrap Around (Default 1: ON) AC[1]: Auto-Increment order 0: Column (CA) first 1: Row (RA) first AC[2]: RID: RA (row address) auto increment direction (L:+1 H:-1) AC[3]: CUM: Cursor update mode, (Default 0: OFF) when CUM=1, CA increment on write only, wrap around suspended AC[4] : Window Program Enable 1 : Enable 0 : Disable AC 5 1H WPC0 WPP0 WPC1 WPP1 8 8 8 8 00H 00H 67H 4FH Window program starting column address. Value range: 0 ~103. Window program starting row address. Value range: 0~79. Window program ending column address. Value range: 0~103. Window program ending row address. Value range: 0~79. For OTP version IC, register WPC[1:0] and WPP[1:0] are also used to control the OTP operation (when OTPC[3]=1). COM scanning end (last COM with full line cycle, 0 based index) Display start (first COM with active scan pulse, 0 based index) Display end (last COM with active scan pulse, 0 based index) Please maintain the following relationship: CEN = the actual number of pixel rows on the LCD - 1 CEN DEN DST+ 9 OTP operation CEN DST DEN 7 7 7 4FH 00H 4FH Revision 0.6 11 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 Description LCD Control: LC[0]: Enable the first FLx2 lines in partial display mode (Default OFF). LC[1]: MX, Mirror X. SEG/Column sequence inversion (Default: OFF) LC[2]: MY, Mirror Y. COM/Row sequence inversion (Default: OFF) LC[4:3]: Line Rate (Klps: Kilo-Line-per-second) 00b: 10.0 Klps 01b: 12.8 Klps 10b: 16.0 Klps 11b: 20.0 Klps (Frame-Rate = Line-Rate / Mux-Rate) LC[5] : RGB filter order (as mapped to SEG1, SEG2, SEG3) 0 : BGR-BGR 1 : RGB-RGB LC[7:6] : Color and input mode for Dither-Enabled: 00b : 256 color mode. 3R-3G-2B (8-bit/RGB) 01b : 4K color mode. 4R-4G-4B (12-bit/RGB) 10b : 56K color mode. 5R-6G-5B (16-bit/RGB) 11b : 221K color mode. 6R-7G-5B (24-bit/RGB) for Dither-Disabled: 00b : 256 color mode. 3R-3G-2B (8-bit/RGB) 01b : 4K color mode. 4R-5G-3B (12-bit/RGB) 10b : 4K color mode. 5R-6G-5B (16-bit/RGB) 11b : 4K color mode. 6R-7G-5B (24-bit/RGB) For data over 4R-5G-3B, each redundant LSB of each color will be truncated. (Example: For R4R3R2R1R0 - G5G4G3G2G1G0 - B4B3B2B1B0, R0, G0, B1, and B0 will be truncated.) LC[9:8] : Partial Display Control Mux-Rate = CEN+1 (DST, DEN not used) 0xb: Disable 10b: Enabled Mux-Rate = CEN+1 11b: Enabled Mux-Rate = DEN-DST+1+LC[0]x2xFL Advanced Program Control. For UltraChip only. Please do not use. OTP option flag 0: No OTP 1: With OTP Name LC Bits 10 Default 090H APC0 APC1 OD OS WS OTPC 5 8 1 1 1 6 0DH 36H - - - 10H OTP programming in-progress OTP Command Succeeded OTP Programming Control: OTP0[2:0] : OTP command 000 : Sleep 001 : Read 010 : Erase 011 : Program 1XX : For UltraChip use only OTP[3] : OTP Enable ( auto clear after OTP command action done ) OTP[4] : Use/Ignore OTP value. 0: Ignore OTP[5] : OTP Command enable 1: Normal OTPM 8 00H OTP Write Mask 12 ES Specifications UC1682 80x104RGB CSTN Controller-Driver COMMAND TABLE The following is a list of host commands supported by UC1682 C/D: 0: Control, 1: Data W/R: 0: Write Cycle, 1: Read Cycle # Useful Data bits - Don't Care Command 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Write Data Byte Read Data Byte Get Status Set Column Address LSB Set Column Address MSB Set Temp. Compensation Set Panel Loading Set Pump Control Set Adv. Program Control (double byte command) Set Scroll Line LSB Set Scroll Line MSB Set Row Address LSB Set Row Address MSB Set VBIAS Potentiometer (double-byte command) Set Partial Display Control Set RAM Address Control Set Fixed Lines Set Line Rate Set All-Pixel-ON Set Inverse Display Set Display Enable Set Color Mask Set LCD Mapping Control Set Color Pattern Set Color Mode System Reset NOP Set Test Control (double byte command) C/D W/R 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 # # ID 0 0 0 0 0 0 # 0 0 0 0 1 # 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 # # MX 0 0 0 0 0 0 # 1 1 1 1 0 # 0 0 0 0 0 0 0 0 1 1 1 1 1 1 D5 D4 D3 # # DE # 0 1 1 0 # # # 0 # 0 1 # 0 0 0 1 0 0 0 0 0 0 0 D2 D1 D0 Action Write 1 byte Read 1 byte Get Status Set CA[3:0] Set CA[6:4] Set TC[1:0] Set PC[1:0] Set PC[3:2] Set APC[R][7:0], R = 0, or 1 Set SL[3:0] Set SL[6:4] Set RA[3:0] Set RA[6:4] Set PM[7:0] Set LC[9:8] Set AC[2:0] Set FL[3:0] Set LC[4:3] Set DC[1] Set DC[0] Set DC[4:2] Set MSK[2:0] Set LC[2:0] Set LC[5] Set LC[7:6] System Reset No operation For testing only. Do not use. Set BR[1:0] AC[3]=0, CA=CR AC[3]=1, CR=CA Set CEN[6:0] Set DST[6:0] Set DEN[6:0] Set WPC0[7:0] Set WPP0[7:0] Set WPC1[7:0] Set WPP1[7:0] Set AC[4] Default N/A N/A N/A 0 0 0 1 11b N/A 0 0 0 0 55H 0: Disable 001b 0 10b 0 0 110b 0 0 0 (BGR) 10b (56K) N/A N/A N/A 11b: 9 AC[3]=0 AC[3]=1 79 0 79 0 0 103 79 0: Disable # # # # MY WA 0 0 0 1 1 0 1 0 1 0 1 1 # # 0 0 0 1 1 0 1 1 0 0 # # 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 # # # # # # WS OD OS # # # # # # 1 # # 0 # # 1 # # 0 0 R # # # # # # # # # # # # # # # 0 0 1 # # # 1 # # # # # # # # 0 # # 1 0 # 1 1 # # # # # # # # # # 0 0 # 1 # # 0 1 0 0 1 1 1 TT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # 1 1 1 1 1 1 1 # 1 # 1 # 1 # 1 # 1 1 1 1 # 1 # 1 # 1 # 1 # 1 # 1 # 1 # 1 1 1 1 # 1 # 1 # 1 # 1 # 1 # 1 # 1 # 0 0 0 1 # 1 # 1 # 1 # 1 # 1 # 1 # 1 # 1 1 1 0 # 0 # 0 # 0 # 0 # 0 # 0 # 1 # 0 1 1 0 # 0 # 0 # 1 # 1 # 1 # 1 # 0 # # 1 1 0 # 1 # 1 # 0 # 0 # 1 # 1 # 0 # # 0 1 1 # 0 # 1 # 0 # 1 # 0 # 1 # # 26 Set LCD Bias Ratio 27 Reset Cursor Update Mode 28 Set Cursor Update Mode 29 Set COM End 30 Set Partial Display Start 31 Set Partial Display End 32 33 Set Window Program Starting Column Address Set Window Programming Starting Row Address Set Window Programming 34 Ending Column Address Set Window Programming 35 Ending Row Address 36 Enable window program * Other than commands listed above, all other bit patterns may result in undefined behavior. 13 Revision 0.6 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 C/D W/R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 1 1 # 1 # 1 # 1 # 1 # D6 0 0 # 1 # 1 # 1 # 1 # D5 1 # 1 # 1 # 1 # 1 # 1 # D4 1 # 1 # 1 # 1 # 1 # 1 # D3 1 # 1 # 0 # 0 # 0 # 0 # D2 0 # 0 # 1 # 1 # 1 # 1 # D1 0 # 0 # 0 # 0 # 1 # 1 # D0 0 # 1 # 0 # 1 # 0 # 1 # Action Set OTP0[5:0] Set OTP1[7:0] Default 0 0 OTP Command 37 Set OTP Operation control 38 Set OTP Write Mask 39 Set VOTP1 Potentiometer 40 Set VOTP2 Potentiometer 41 Set OTP Write Timer 42 Set OTP Read Timer Shared with Window Programming commands N/A * * * Other than commands listed above, all other bit patterns may result in undefined behavior. The OTP commands listed above should only be used with OTP version of UC1682. Command 39~42 are shared with command 32~35, and they have exactly the same code. The interpretation of these four commands depends on register OTPC[3]. When OTPC[3]=0, they are interpreted as Window Programming commands. When OTPC[3]=1, they are OTP Control commands. OTPM and PM are actually the same register. The usage of this register is determined by OTPC[3] in similar ways as Command 39~42. After OTP-ERASE or OTP-PROGRAM operation (Set OTPC[3]=1) , always a) remove TST4 power source; b) Do a full Vdd ON-OFF cycle; before resuming normal operation. * * 14 ES Specifications UC1682 80x104RGB CSTN Controller-Driver COMMAND DESCRIPTION (1) WRITE DATA TO DISPLAY MEMORY Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Write data 1 0 8bits data write to SRAM UC1682 will convert input RAM data to 12-bits of RGB data. Please refer to command (22) Set Color Mode for detail data write sequence. The format of 12 bits RGB data is as following: D11 D10 R (2) READ DATA FROM DISPLAY MEMORY Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Read data 1 1 8bits data from SRAM Each RGB triplet is stored as 12-bit in the display RAM. Each 12 bits RGB data takes 2 RAM read cycles. The data read will start with the high byte D[11:4] and then low byte {D[3:0],4'b0000}. The read out RGB data is after-dither for 56K color and 221K color mode and after-extension for 256 color mode. R3 R2 R1 R0 G4 G3 G2 G1 G0 B2 B1 B0 0 0 0 0 D9 D8 D7 D6 G D5 D4 D3 D2 B D1 D0 1st Read 2nd Read Write/Read Data Byte (command 1/2) operation uses internal Row Address register (RA) and Column Address register (CA). RA and CA can be programmed by issuing Set Row Address and Set Column Address commands. If wrap-around (WA, AC[0]) is OFF (0), CA will stop incrementing after reaching the CA boundary, and system programmers need to set the values of RA and CA explicitly. If WA is ON (1), when CA reaches end of column address, CA will be reset to 0 and RA will be increased or decreased, depending on the setting of Row Increment Direction (RID, AC[2]). When RA reaches the boundary of RAM (i.e. RA = 0 or 79), RA will be wrapped around to the other end of RAM and continue. (3) GET STATUS Action Get Status Status flag definitions: ID: MX: MY: WA: DE: WS : OD: OS : C/D W/R D7 0 1 ID D6 D5 D4 D3 D2 D1 D0 MX MY WA DE WS OD OS Provide access to ID pin connection status. Status of register LC[1], mirror X. Status of register LC[2], mirror Y. Status of register AC[0]. Automatic column/row wrap around. Display enable flag. DE=1 when display is enabled OTP Command Succeeded OTP Option (Yes/No) OTP action status (4) SET COLUMN ADDRESS Action Set Column Address LSB CA[3:0] C/D W/R D7 0 0 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CA3 CA2 CA1 CA0 0 0 0 1 Set Column Address MSB CA[6:4] 0 0 - CA6 CA5 CA4 Set SRAM column address for read/write access. CA is counted in RGB triplets, not individual SEG electrode. CA value range: 0~103 Revision 0.6 15 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 (5) SET TEMPERATURE COMPENSATION Action C/D W/R D7 D6 D5 D4 0 D3 0 D2 1 D1 D0 0 0 1 Set Temperature Comp. TC[1:0] 0 0 Set VBIAS temperature compensation coefficient (%-per-degree-C) Temperature compensation curve definition: o o 01b= -0.10%/ C 00b= -0.05%/ C (6) SET PANEL LOADING Action C/D W/R D7 D6 D5 D4 0 D3 1 D2 0 D1 D0 0 0 1 Set Panel Loading PC[1:0] 0 0 Set PC[1:0] according to the capacitance loading of LCD panel. Panel loading definition: (7) SET PUMP CONTROL Action C/D W/R D7 D6 0 D5 1 D4 0 D3 1 D2 1 D1 D0 0 Set Pump Control PC[3:2] 0 0 Set PC[3:2] to program the build-in charge pump stages. Pump control definition: 00b=External VLCD 11b= Internal VLCD (standard) PC3 PC2 00b 9nF 01b= 9~12nF PC1 PC0 11b= 16~22nF TC1 TC0 10b= -0.15%/ C o 11b= -0.20%/ C o 10b= 12~16nF (8) SET ADVANCED PROGRAM CONTROL Action Set APC[1:0] (Double byte command) For UltraChip only. Please do NOT use. (9) SET SCROLL LINE Action Set Scroll Line LSB SL[3:0] Set Scroll Line MSB SL[6:4] Set the scroll line number. C/D W/R D7 0 0 0 0 0 0 D6 1 1 D5 0 0 D4 0 1 D3 D2 D1 D0 SL3 SL2 SL1 SL0 SL6 SL5 SL4 C/D W/R D7 0 0 0 0 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 R APC register parameter Scroll line setting will scroll the displayed image up by SL rows. The valid value for SL is between 0 (no scrolling) and (79-2xFL). FL is the register value programmed by Set Fixed Lines command. Image row 0 .......... Image row N .......... Image row N .......... Image row 79 Image row 0 ......... Image row 79 Image row N-1 SL=0 SL=N 16 ES Specifications UC1682 80x104RGB CSTN Controller-Driver (10) SET ROW ADDRESS Action Set Row Address LSB RA [3:0] C/D W/R D7 0 0 0 0 0 D6 1 1 D5 1 1 D4 0 1 D3 D2 D1 D0 RA3 RA2 RA1 RA0 RA6 RA5 RA4 Set Row Address MSB RA [6:4] 0 Set SRAM row address for read/write access. Possible value = 0~79 (11) SET VBIAS POTENTIOMETER Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 1 Set VBIAS Potentiometer. PM [7:0] 0 0 (Double byte command) 0 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Program VBIAS Potentiometer (PM[7:0]). See section LCD VOLTAGE SETTING for more detail. Effective range: 0 ~ 255 (12) SET PARTIAL DISPLAY CONTROL Action C/D W/R D7 D6 0 D5 0 D4 0 D3 0 D2 1 D1 D0 1 Set Partial Display Enable LC [9:8] 0 0 This command is used to enable partial display function. LC9 LC8 LC[9:8] : 0Xb: Disable Partial Display, Mux-Rate = CEN+1 (DST, DEN not used.) 10b: Enable Partial Display, Mux-Rate = CEN+1 11b: Enable Partial Display, Mux-Rate = DEN-DST+1+LC[0]x2xFL (13) SET RAM ADDRESS CONTROL Action Set AC [2:0] C/D W/R D7 0 0 1 D6 0 D5 0 D4 0 D3 1 D2 D1 D0 AC2 AC1 AC0 Program registers AC[2:0] for RAM address control. AC[0]: WA, Automatic column/row wrap around. 0: CA or RA (depends on AC[1]= 0 or 1) will stop incrementing after reaching boundary 1: CA or RA (depends on AC[1]= 0 or 1) will restart, and RA or CA will increment by one step. AC[1]: Auto-Increment order 0 : column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+/-1). 1 : row (RA) increment (+/-1) first until RA reach RA boundary, then CA will increment by (+1). AC[2]: RID, row address (RA) auto increment direction ( 0/1 = +/- 1 ) When WA=1 and CA reaches CA boundary, RID controls whether row address will be adjusted by +1 or -1. AC[2:0] controls the auto-increment behavior of CA and RA. When Window Program is enabled (AC[4]=ON), see command description (32) ~ (36) for more details. If WPC[1:0] and WPP[1:0] values are the default values, the behavior of CA, RA auto-increment will be the same, no matter what the setting of AC[4] is. Revision 0.6 17 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 (14) SET FIXED LINES Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 FL3 FL2 FL1 FL0 Set Fixed Lines FL [3:0] 0 0 The fixed line function is used to implement the partial scroll function by dividing the screen into scroll and fixed area. Set Fixed Lines command will define the fixed area, which will not be affected by the SL scroll function. The fixed area covers the top 2xFL rows for mirror Y (MY) is 0 and bottom 2xFL rows for MY=1. One example of the visual effect on LCD is illustrated in the figure below. Fixed Area 1 Scroll Area 1 (2xFL) Scroll Area Fixed Area 80 MY = 0 (2xFL) MY = 1 80 When partial display mode is activated, the display of these 2xFL lines is also controlled by LC[0]. ]. Before turning on LC[0], please make sure MY=0 DST >= FLx2 DEN <= CEN. MY=1 DST >= 0 DEN <= CEN-FLx2 (15) SET LINE RATE Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 0 LC4 LC3 Set Line Rate LC [4:3] 0 0 Program LC [4:3] for line rate setting (Frame-Rate = Line-Rate / Mux-Rate). The line rate is automatically scaled down by 1/2 and 1/3 at Mux-Rate = 38 and 24. The following are line rates at Mux Rate = 39 ~ 80. 00b: 10.0 Klps 01b: 12.8 klps (Klps: Kilo-Line-per-second) (16) SET ALL PIXEL ON Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 1 0 DC1 Set All Pixel ON DC [1] 0 0 Set DC[1] to force all SEG drivers to output ON signals. This function has no effect on the existing data stored in display RAM. (17) SET INVERSE DISPLAY Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 1 1 DC0 Set Inverse Display DC [0] 0 0 Set DC[0] to force all SEG drivers to output the inverse of the data (bit-wise) stored in display RAM. This function has no effect on the existing data stored in display RAM. 10b: 16.0 Klps 11b: 20.0 Klps 18 ES Specifications UC1682 80x104RGB CSTN Controller-Driver (18) SET DISPLAY ENABLE Action C/D W/R D7 1 D6 0 D5 1 D4 0 D3 1 D2 D1 D0 Set Display Enable DC [4:2] 0 0 This command is for programming register DC[4:2]. DC4 DC3 DC2 When DC[2] is set to 0, the IC will put itself into Sleep mode. All drivers, voltage generation circuit and timing circuit will be halted to conserve power. When DC[2] is set to 1, UC1682 will first exit from Sleep mode, restore the power and then turn on COM drivers and SEG drivers. There is no other explicit user action or timing sequence required to enter or exit the Sleep mode. DC[3] controls the gray shade modulation modes. UC1682 has two gray shade modulation modes: an 8sahde mode and a 32-shade mode. The modulation curves are shown below. Horizontal axes are the gray shade data. The vertical axes are the ON-OFF ratio. 9/9 is 100% ON for 8-shade mode, 51/51 is 100% ON for 32-shade mode. 9 50 45 40 6 35 30 25 20 3 15 10 5 0 1 2 3 4 5 6 7 8 0 1 4 7 10 13 16 19 22 25 28 31 DC[4] enables dither function. Refer to (22) Set Color Mode for more information. 0b: Disable 1b: Enable Revision 0.6 19 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 (19) SET COLOR MASK Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 0 Set Color Mask MSK [2:0] 0 0 MSK[2:0] This command is used for program MSK[2:0] which will control whether the input RGB data will be blocked from updating RGB data in the RAM. (1: Block, 0: Normal. MSK[2:0] = {MSK_R, MSK_G, MSK_B}) Example: Let color mode = 256 color, MSK[2:0] = 100b (MSK_R = 1, MSK_G = 0, MSK_B = 0). There is one pixel to be updated, and the original data for the pixel is 11100110b (RRR-GGG-BB). Suppose the new input RGB data is 00000000b, since R is masked, the data for the pixel would be updated as 11100000b. (20) SET LCD MAPPING CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 0 MY MX LC0 Set LCD Mapping Control LC [2:0] 0 0 This command is used for program LC[2:0] for COM (row) mirror (MY), SEG (column) mirror (MX). LC[2] controls Mirror Y (MY): MY is implemented by reversing the mapping order between RAM and COM electrodes. The data stored in RAM is not affected by MY command. MY will have immediate effect on the display image. LC[1] controls Mirror X (MX): MX is implemented by selecting the CA or 103-CA as write/read (from host interface) display RAM column address so this function will only take effect after rewriting the RAM data. LC[0] controls whether the soft icon section (0~ 2xFL) is display or not during partial display mode. (21) SET COLOR PATTERN Action Set Color Pattern LC [5] UC1682 supports on-chip swapping of R C/D W/R D7 D6 D5 D4 D3 D2 D1 0 D0 LC5 1 1 0 1 0 0 0 0 B data mapping to the SEG drivers. SEG304 SEG311 SEG312 LC[5] SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 ... 0 B G R B G R ... B G R 1 R G B R G B ... R G B The definition of R/G/B input data is determined by LC[7:6], as described in Set Color Mode below. 20 ES Specifications UC1682 80x104RGB CSTN Controller-Driver (22) SET COLOR MODE Action C/D W/R D7 D6 D5 D4 D3 D2 1 D1 D0 1 1 0 1 0 Set Color Mode LC [7:6] 0 0 Program color mode and RGB input pattern. Color mode (LC[7:6]) definition: LC7 LC6 Dither Options: DC[4]=1b enables dither function. Refer to (18) Set Display Enable for more information. LC[7:6] = 00b ( RRR-GGG-BB, 256 color ) One byte of input data is extended and stored to 12 RAM bits. Data Write Sequence 1st Byte Write Data D[7:0] R2 R1 R0 G2 G1 G0 B1 B0 LC[7:6] = 01b ( RRRR-GGGG-BBBB, 4K color ) 1-bit extension for G, 1-bit dither for B. 12 bits of input data is stored to 12 RAM bits. 3 bytes of input data will be merged into 2 sets of RGB data. Data Write Sequence 1st Byte Write Data nd 2 Byte Write Data rd 3 Byte Write Data D[7:0] R3 R2 B3 B2 G3 G2 R1 B1 G1 R0 B0 G0 G3 R3 B3 G2 R2 B2 G1 R1 B1 G0 R0 B0 LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 56K color ) 1-bit dither for R/G, 2-bit dither for B. 16 bits input data dithered to 12 RAM bits. Data Write Sequence 1st Byte Write Data 2nd Byte Write Data D[7:0] R4 R3 G2 G1 R2 G0 R1 B4 R0 B3 G5 B2 G4 B1 G3 B0 LC[7:6] = 11b ( RRRRRR-GGGGGGG-BBBBB, 221K color ) 2-bit dither per color. 18 out of 24 bits input data is dithered to 12 RAM bits. Data Write Sequence 1st Byte Write Data 2nd Byte Write Data 3rd Byte Write Data Data Read Sequence for LC[7:6] = 0. Data Read Sequence D[7:0] 1st Byte Read Data R2 R1 R0 RM 2nd Byte Read Data GM1 B2 B1 B0 R/G/B: the input Red/Green/Blue data. R/GMN: the Red/Green bits mapped from RGB input data. for LC[7:6] = 1, 2, 3. G2 0 G1 0 G0 0 GM2 0 D[7:0] R5 R4 G6 G5 B4 B3 R3 G4 B2 R2 G3 B1 R1 G2 B0 R0 G1 --G0 ----- Data Read Sequence D[7:0] st 1 Byte Read Data RD3 RD2 RD1 RD0 GD4 nd 2 Byte Read Data GD0 BD2 BD1 BD0 0 R/G/BDN : the N-th bit of after-dither Red/Green/Blue input data Note: GD3 0 GD2 0 GD1 0 For system designers who want to use their own dithering algorithm, please set LC[7:6] = 10b (56k color mode) and use the following input pattern to bypass on-chip dithering algorithm: R3-R2-R1-R0-1-G4-G3-G2-G1-G0-1-B2-B1-B0-1-0 Revision 0.6 21 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 No-Dither Options: DC[4]=0b disables dither function. Refer to (18) Set Display Enable for more information. LC[7:6] = 00b ( RRR-GGG-BB, 256 color ) One byte of input data is extended and stored to 12 RAM bits. Data Write Sequence 1st Byte Write Data D[7:0] R2 R1 R0 G2 G1 G0 B1 B0 LC[7:6] = 01b ( RRRR-GGGGG-BBB, 4K color ) 12 bits of input data is stored to 12 RAM bits. 3 bytes of input data will be merged into 2 sets of RGB data. Data Write Sequence st 1 Byte Write Data 2nd Byte Write Data 3rd Byte Write Data D[7:0] R3 R2 G0 B2 G4 G3 R1 B1 G2 R0 B0 G1 G4 R3 G0 G3 R2 B2 G2 R1 B1 G1 R0 B0 LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 56K color ) 1-bit truncation for R/G, 2-bit for B. 16 bits input data truncated to 12 RAM bits. Data Write Sequence 1st Byte Write Data nd 2 Byte Write Data D[7:0] R4 R3 G2 G1 R2 G0 R1 B4 R0 B3 G5 B2 G4 B1 G3 B0 LC[7:6] = 11b ( RRRRRR-GGGGGGG-BBBBB, 221K color ) 2-bit truncation for per color. 18 out of 24 bits input data is truncated to 12 RAM bits. Data Write Sequence st 1 Byte Write Data nd 2 Byte Write Data 3rd Byte Write Data Data Read Sequence for LC[7:6] = 0. Data Read Sequence D[7:0] 1st Byte Read Data R2 R1 R0 RM 2nd Byte Read Data GM1 B2 B1 B0 R/G/B: the input Red/Green/Blue data. R/GMN: the Red/Green bits mapped from RGB input data. for LC[7:6] = 1, 2, 3. G2 0 G1 0 G0 0 GM2 0 D[7:0] R5 R4 G6 G5 R4 R3 R3 G4 R2 R2 G3 R1 R1 G2 R0 R0 G1 --G0 ----- Data Read Sequence D[7:0] 1st Byte Read Data RT3 RT2 RT1 RT0 GT4 GT3 2nd Byte Read Data GT0 BT2 BT1 BT0 0 0 R/G/BTN : the N-th bit of after-truncated Red/Green/Blue input data (23) SYSTEM RESET Action C/D W/R D7 D6 D5 D4 D3 D2 GT2 0 GT1 0 D1 D0 1 1 1 0 0 0 1 0 System Reset 0 0 This command will activate the system reset. Control register values will be reset to their default values. Data stored in RAM will not be affected. 22 ES Specifications UC1682 80x104RGB CSTN Controller-Driver (24) NOP Action C/D W/R D7 0 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 No Operation 0 This command is used for "no operation". (25) SET TEST CONTROL Action Set TT (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 D0 TT 0 0 Testing parameter This command is used for UltraChip production testing. Please do not use. (26) SET LCD BIAS RATIO Action Set Bias Ratio BR [1:0] Bias ratio definition: 00b= 5 01b=7 (27) RESET CURSOR UPDATE MODE Action C/D W/R D7 D6 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 Reset Cursor Update Mode AC[3]=0 1 1 0 0 CA=CR This command is used to reset cursor update mode function. (28) SET CURSOR UPDATE MODE Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 1 1 1 1 Set AC[3]=1 CR=CA 0 0 This command is used for set cursor update mode function. When cursor update mode is set, UC1682 will update register CR with the value of register CA. The column address CA will increment with write RAM data operation but the address wraps around will be suspended no matter what WA setting is. However, the column address will not increment in read RAM data operation. The set cursor update mode can be used to implement "write after read RAM" function. The column address (CA) will be restored to the value, which is before the set cursor update mode command, when resetting cursor update mode. The purpose of this pair of commands and their features is to support "write after read" function for cursor implementation. (29) SET COM END Action Set CEN (Double byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1 C/D W/R D7 0 0 10b=8 1 D6 1 D5 1 D4 0 D3 1 D2 0 D1 D0 BR1 BR0 11b=9 CEN register parameter This command programs the ending COM electrode. CEN defines the number of used COM electrodes, and it should correspond to the number of pixel-rows in the LCD. Revision 0.6 23 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 (30) SET PARTIAL DISPLAY START Action Set DST (Double byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 1 D0 0 DST register parameter This command programs the starting COM electrode, which has been assigned a full scanning period and will output an active COM scanning pulse. (31) SET PARTIAL DISPLAY END Action Set DEN (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 1 D0 1 DEN register parameter This command programs the ending COM electrode, which has been assigned a full scanning period and will output an active COM scanning pulse. CEN, DST, and DEN are 0-based index of COM electrodes. They control only the COM electrode activity, and do not affect the mapping of display RAM to each COM electrodes. The image displayed by each pixel row is therefore not affected by the setting of these three registers. When LC[9]=1, two partial display modes are possible with UC1682: LC[8]=1: ON-OFF only, ultra-low-power mode (if Mux-Rate 32, set BR=5). LC[8]=0: Full gray shade low power mode (BR and PM stays the same) When LC[9:8]=11b, the Mux-Rate is narrowed down to just the range between DST and DEN. When MuxRate is under 32, set BR=5, PC[3:2]=01b, and adjust PM to reduce VLCD and achieve the lowest power consumption. When LC[9:8]=10b, the Mux-Rate is still CEN+1. This is achieved by suppressing only the scanning pulses, but not the scanning time slots, for COM electrodes that is outside of DST~DEN. Under this mode, the gray-scale quality of the display is preserved, while the power can be reduced significantly. In either case, DST/DEN defines a small subsection of the display which will remain active while shutting down all the rest of the display to conserve energy. 0 DST DEN CEN Pulse Disable: Pulse Enable: Not Scanned: 79 (32) SET WINDOW PROGRAM STARTING COLUMN ADDRESS Action Set WPC0 (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 WPC0[7:0] register parameter This command is to program the starting column address of RAM program window. 24 ES Specifications UC1682 80x104RGB CSTN Controller-Driver (33) SET WINDOW PROGRAM STARTING ROW ADDRESS Action Set WPP0 (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1 WPP0 register parameter This command is to program the starting row address of RAM program window. (34) SET WINDOW PROGRAM ENDING COLUMN ADDRESS Action Set WPC1 (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 1 D0 0 WPC1[7:0] register parameter This command is to program the ending column address of RAM program window. (35) SET WINDOW PROGRAM ENDING ROW ADDRESS Action Set WPP1 (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 1 D0 1 WPP1 register parameter This command is to program the ending row address of RAM program window. (36) SET WINDOW PROGRAM ENABLE Action Set Window Program Enable AC[4] C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 1 D2 0 D1 0 D0 AC4 This command is to enable the Window Program Function. Window Program Enable should always be reset when changing the window program boundary and then set right before starting the new boundary program. Window Program Function can be used to refresh the RAM data in a specified window of SRAM address. When window programming is enabled, the CA and RA increment and wrap around will be automatically adjusted, and therefore allow effective data update within the window. The direction of Window Program will depend on the WA (AC[0]), RID (AC[2]), auto-increment order (AC[1]) and MX (LC[1]) register setting. WA decides whether the program RAM address advances to next row/column after reaching the specified window column / row boundary. RID controls the RAM address incrementing from WPP0 toward WPP1 (RID=0) or reverse the direction (RID=1). Auto-increment order directs the RAM address increment vertically (AC[1]=1) or horizontally (AC[1]=0). MX results the RAM column address incrementing from 103-WPC0 to 103-WPC1 (MX=1) or WPC0 to WPC1 (MX=0). Revision 0.6 25 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 Auto-increment order = 0 MX=0 RID = 0 (WPP0,WPC0) (WPP1,WPC1) Auto-increment order = 1 MX=0 RID = 0 (WPP0,WPC0) (WPP1,WPC1) Auto-increment order = 0 MX=0 RID = 1 (WPP0,WPC0) (WPP1,WPC1) Auto-increment order = 0 MX=1 RID = 0 (WPP0,103-WPC0) (WPP1,103-WPC1) 26 ES Specifications UC1682 80x104RGB CSTN Controller-Driver Auto-increment order = 1 MX=0 RID = 1 (WPP0,WPC0) (WPP1,WPC1) Auto-increment order = 1 MX=1 RID = 0 (WPP0,103-WPC0) (WPP1,103-WPC1) Auto-increment order = 0 MX=1 RID = 1 (WPP0,103-WPC0) (WPP1,103-WPC1) Auto-increment order = 1 MX=1 RID = 1 (WPP0,103-WPC0) (WPP1,103-WPC1) Revision 0.6 27 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 (37) SET OTP CONTROL Action Set OTPC (Double byte command) C/D W/R D7 0 0 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 OTP0 register parameter This command is for OTP operation control: OTPC[2:0] : OTP command 000 : Sleep 010 : OTP Erase 1XX : For UltraChip use only. 001 : OTP Read 011 : OTP Program OTPC[3] : OTP Enable (automatically cleared each time after OTP command is done) OTPC[4] : OTP value valid ( ignore OTP value when L ) OTPC[5] : OTP operation mode - Set [5] before OTP external V connection (38) SET OTP WRITE MASK Action Set OTPM (Double byte command) C/D W/R D7 0 0 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1 OTP1 register parameter This command is enable write to each of the 8 individual OTP bits (39) SET VOTP1 POTENTIOMETER Action Set OTP2 (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 OTP2 register parameter This command is for fine tuning VOPT1 setting (use with BR=00) (40) SET VOTP2 POTENTIOMETER Action Set OTP3 (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1 OTP3 register parameter This command is for fine tuning VOTP2 PM setting (use with BR=10) (41) SET OTP WRITE TIMER Action Set OTP4 (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 1 D0 0 OTP4 register parameter (42) SET OTP READ TIMER Action Set OTP5 (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 1 D0 1 OTP5 register parameter 28 ES Specifications UC1682 80x104RGB CSTN Controller-Driver LCD VOLTAGE SETTING MULTIPLEX RATES Multiplex Rate is completely software programmable in UC1682 via registers CEN, DST, DEN, and partial display control LC[9:8]. Combined with low power partial display mode and a low bias ratio of 5, UC1682 can support wide variety of display control options. For example, when a system goes into stand-by mode, a large portion of LCD screen can be turned off to conserve power. BIAS RATIO SELECTION Bias Ratio (BR) is defined as the ratio between VLCD and VBIAS, i.e. BR = VLCD /VBIAS, where VBIAS = VB1+ - VB1- = VB0+ - VB0-. The theoretical optimum Bias Ratio can be estimated by Mux + 1 . BR of value 15~20% lower/higher than the optimum value calculated above will not cause significant visible change in image quality. Due to the nature of STN operation, an LCD designed for good gray-shade performance at high Mux Rate (e.g. MR=80), can generally perform very well as a black and white display, at lower Mux Rate. However, it is also true that such technique generally can not maintain LCD's quality of gray shade performance, since the contrast of the LCD will increase as Mux Rate decreases, and the shades near the two ends of the spectrum will start to lose visibility. UC1682 supports four BR as listed below. BR can be selected by software program. BR Bias Ratio 0 5 1 7 2 8 3 9 VLCD GENERATION VLCD may be supplied either by internal charge pump or by external power supply. The source of VLCD is controlled by PC[3:2]. For good product reliability, it is recommended to keep VLCD under 12V over the entire operating range. When VLCD is generated internally, the voltage level of VLCD is determined by three control registers: BR (Bias Ratio), PM (Potentiometer), and TC (Temperature Compensation), with the following relationship: V LCD = (CV 0 + C PM x PM ) x (1 + (T - 25) x CT %) where CV0 and CPM are two constants, whose value depends on the setting of BR register, as illustrated in the table on the next page, PM is the numerical value of PM register, T is the ambient temperature in OC, and CT is the temperature compensation coefficient as selected by TC register. VLCD FINE TUNING Gray shade and color STN LCD is sensitive to even a 1% mismatch between IC driving voltage and the VOP of LCD. However, it is difficult for LCD makers to guarantee such high precision matching of parts from different venders. It is therefore necessary to adjust VLCD to match the actual VOP of the LCD. For the best results, software or OTP based VLCD adjustment is the recommended method for VLCD fine tuning. For applications where mechanical manual fine tuning of VLCD becomes necessary, then VBIAS pin may be used with an external trim pot to fine tune the VLCD. LOAD DRIVING STRENGTH The power supply circuit of UC1682 is designed to handle LCD panels with load capacitance up to ~20nF when VDD2 = 2.5V. For larger LCD panels use higher VDD and COF packaging. 20nF is also the recommended limit for LCD panel size for COG applications. Table 1: Bias Ratios TEMPERATURE COMPENSATION Four (4) different temperature compensation coefficients can be selected via software. The four coefficients are given below: TC % per C o 0 -0.05 1 -0.10 2 -0.15 3 -0.20 Table 2: Temperature Compensation Revision 0.6 29 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 VLCD QUICK REFERENCE 14 13 12 11 10 VLCD 9 8 7 6 5 4 0 32 64 96 128 PM VLCD-PM relationship for different BR setting at 25oC. 160 192 224 256 BR 5 7 8 9 CV0 (V) 4.474 6.206 7.070 7.931 CPM (mV) 12.50 17.50 20.00 22.50 PM 0 255 0 255 0 255 0 255 VLCD (V) 4.47 7.66 6.21 10.67 7.07 12.17 7.93 13.67 Note: 1. 2. For good product reliability, keep VLCD under 10.3V at room temperature, and keep VLCD under 10.5V under all temperature and operating conditions. The integer values of BR above are for reference only and probably have slight shift. 30 ES Specifications UC1682 80x104RGB CSTN Controller-Driver HI-V GENERATOR AND BIAS REFERENCE CIRCUIT VDD VDD VDD2/VDD3 VB0+ SB0+ CB0 VDD2 VDD3 VB0SB0- UC1682 VB1+ SB1+ CB1 VB1SB1- CB1+ (OPTIONAL) 30pf for applications with VLCD over 11v VLCDOUT VLCDIN VSS VSS2 CL RL (OPTIONAL) FIGURE 3: Reference circuit using internal Hi-V generator circuit VDD VDD VDD2/VDD3 VDD2 VDD3 VB0+ SB0+ CB0 VB0SB0VB1+ SB1+ UC1682 R1 CB1 VB1SB1- VR VBIAS CB1+ (OPTIONAL) 10~30pf for applications with VLCD over 11v CBIAS VLCDOUT VLCDIN VSS VSS2 CL RL (OPTIONAL) FIGURE 4: Reference circuit using external Bias source Note Sample component values: (The illustrated circuit and component values are for reference only. Please optimize for specific requirements of each application.) 150 ~ 250x LCD load capacitance or 2.2F (2V), whichever is higher. CB: CL: 5nF ~ 50nF (16V) is appropriate for most applications. RL: 3 ~ 10M , RC time constant of CL x RL should be roughly 0.2~1sec 1M VR: R1: 330K CBIAS: 10nF ~ 0.1uF is the recommended default value (not required for OTP version). Revision 0.6 31 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 LCD DISPLAY CONTROLS CLOCK & TIMING GENERATOR UC1682 contains a built-in system clock. All required components for the clock oscillator are built-in. No external parts are required. Four different line rates are provided for system design flexibility. The line rate is controlled by register LC[4:3]. When Mux-Rate is above 38, frame rate is calculated as: Frame Rate = Line-Rate / Mux-Rate. When Mux-Rate is lowered to 38 (and 24), line rate will be scaled down by 2 (and 3) times automatically reduce power consumption. Flicker-free frame rate is dependent on LC material and gray-shade modulation scheme. Frame rate 175Hz is recommended for 32-shade mode. Choose lower frame rate for lower power, and choose higher frame rate to improve LCD contrast and minimize flicker. When switching from 32-shade modulation to 8shade modulation, line rate will be scaled down automatically by ~30%. Under most situations, flicker behavior is similar between these two different modulation schemes. When switching from 32-shade modulation to 8shade modulation, line rate will be scaled down automatically by ~35%. Under most situations, flicker behavior is similar between these two different modulation schemes. However, it is always recommended to test each mode to make sure flicker behavior is acceptable DRIVER MODES COM and SEG drivers can be in either Idle mode or Active mode, controlled by Display Enable flag (DC[2]). When SEG drivers are in Idle mode, they will be connected together to ensure zero DC condition on the LCD. DRIVER ARRANGEMENTS The naming conventions are: COM(x), where x=1~80, refers to the COM driver for the x-th row of pixels on the LCD panel. The mapping of COM(x) to LCD pixel rows is fixed and it is not affected by SL, CST, CEN, DST, DEN, MX or MY settings. DISPLAY CONTROLS There are three groups of display control flags in the control register DC: Driver Enable (DE), AllPixel-ON (APO) and Inverse (PXV). DE has the overriding effect over PXV and APO. PARTIAL DISPLAY UC1682 provides flexible control of Mux Rate and active display area. Please refer to command Set COM End, Set Partial Display Start, and Set Partial Display End for more detail. GRAY-SHADE MODULATION MODE UC1682 has two gray-shade modulation modes: 32-shade and 8-shade. The 8-shade mode will consume ~30% less power than the 32-shade mode, and can be used for situations where power consumption is more critical than color fidelity. Changing gray-shade modulation mode does not affect the content of SRAM display buffer, and the image data will remain the same after switching back and forth between 8-shade mode and 32-shade mode. DRIVER ENABLE (DE) Driver Enable is controlled by the value of DC[2] via Set Display Enable command. When DC[2] is set to OFF (logic "0"), both COM and SEG drivers will become idle and UC1682 will put itself into Sleep mode to conserve power. When DC[2] is set to ON, the DE flag will become "1", and UC1682 will first exit from Sleep mode, restore the power (VLCD, VD etc.) and then turn on COM and SEG drivers. ALL PIXELS ON (APO) When set, this flag will force all SEG drivers to output ON signals, disregarding the data stored in the display buffer. This flag has no effect when Display Enable is OFF and it has no effect on data stored in RAM. INVERSE (PXV) When this flag is set to ON, SEG drivers will output the inverse of the value it received from the display buffer RAM (bit-wise inversion). This flag has no impact on data stored in RAM. PARTIAL SCROLL Control register FL specifies a region of rows which are not affected by the SL register. Since SL register can be used to implement scroll function. The FL register can be used to implement fixed region when the other part of the display is scrolled by SL. 32 ES Specifications UC1682 80x104RGB CSTN Controller-Driver INPUT COLOR FORMATS UC1682 supports the following four different input color formats. 256C (8-bit/RGB): This is the most compact color mode, and is intended to minimize the bus cycle required to refresh the display buffer. Onchip extension circuit will automatically expand the input RGB data into on-chip RAM buffer format. 4KC (12-bit/RGB): In this color mode, G will be extended while B will be dithered, and the input data will be converted into 4R-5G-3B format before they are stored to display RAM. 56KC (16-bit/RGB): On-chip dither engine will convert the input data into internal 12-bit-perRGB pixel format and store it to on-chip display RAM. This is the default mode. 221KC (24-bit/RGB): On-chip dither engine will convert input data into 4R-5G-3B format and store it to on-chip display RAM. This mode provides the smoothest shades and the most vivid color in the LCD. Changing color mode does not affect the content already stored in the display buffer RAM. Users can use several color modes together in real time. For example, the menu portion can be painted in 256-color mode for fast update speed, and then switch to 221K-color mode, together with window programming option, and take advantage of builtin dither engine to produce smooth graphics images. LAYOUT CONSIDERATIONS FOR COM SIGNALS Since the COM scanning pulse of UC1682 can be as short as 30S, it is critical to control the RC delay of COM signal to minimize distortion of COM scanning pulse. For the best image quality, limit the worst case of RC delay of COM signal as calculated below. (RROW / 2.7+ RCOM + ROUT) x CROW < 2S where CROW : LCD loading capacitance of one row of pixels. It can be calculated by CLCD/Mux-Rate, where CLCD is the LCD panel capacitance. ITO resistance over one row of pixels within the active area COM routing resistance from IC to the active area COM output impedance In addition, please make sure | RCMAX - RCMIN | < 0.3 x RCMAX so that the COM distortions on the top of the screen to the bottom of the screen are uniform. LAYOUT CONSIDERATIONS FOR SEG SIGNALS Excessive SEG signal RC decay can cause image dependent changes of medium gray shades and sharply increase of SEG direction crosstalk. Please limit the worst case of SEG signal RC delay as calculated below. (RCOL /2.7 + RSEG) x CCOL < 0.5S where CCOL: LCD loading capacitance of one pixel column. It can be calculated by CLCD / #_of column, CLCD is the LCD panel capacitance. ITO resistance over one column of pixels within the active area SEG routing resistance from IC to the active area + SEG driver output impedance RCOL: RSEG: LAYOUT CONSIDERATIONS FOR SEG SIGNALS Excessive SEG signal RC decay can cause image dependent changes of medium gray shades and sharply increase of SEG direction crosstalk. For good image quality, please limit the worst case of SEG signal RC delay as calculated below. (RCOL /2.7 + RSEG) x CCOL < 0.4S where CCOL: LCD loading capacitance of one pixel column. It can be calculated by CLCD / #_of column, CLCD is the LCD panel capacitance. ITO resistance over one column of pixels within the active area RCOL: SEG routing resistance from IC to the RSEG: active area + SEG driver output impedance RROW : RCOM: ROUT: Revision 0.6 33 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 RAM W/R POL COM1 COM2 COM3 SEG1 SEG2 FIGURE 5: COM and SEG Driving Waveform 34 ES Specifications UC1682 80x104RGB CSTN Controller-Driver HOST INTERFACE As summarized in the table below, UC1682 supports two parallel bus protocols, in either 8-bit or 4-bit bus width, and three serial bus protocols. Bus Type Width Access BM[1:0] D[7:6] CS[1:0] CD WR0 WR1 8080 8-bit 10 Data 4-bit 8-bit Read/Write 00 11 0X Data 6800 4-bit 01 00 0X 10 Chip Select Control/Data _ _ Designers can either use parallel bus to achieve high data transfer rate, or use serial bus to create compact LCD modules. S8 (4wr) S8uc (3wr) Serial Write Only 00 11 S9 (3wr) Control & Data Pins 01 1X - ___ __ WR ___ __ R/W EN - - - D0=SCK, D3=SDA RD D[5:4] Data - Data - D[3:0] Data Data Data Data * Connect unused control pins and data bus pins to VDD or VSS CS Disable Interface 8-bit 4-bit S8 or S9 S8uc * * * * * - CS Init bus state - - - CD 1<=>0 Init bus state - CD 1=>0 init color mapping RESET Init bus state RESET init color mapping CS disable bus interface - CS can be used to disable Bus Interface Write / Read Access. CD refers to CD transitions within valid CS window. CD = 0 means write command or read status. CS / CD Sync / RESET can be used to initialize bus state machine (like 4 bits / S8 / S9). RESET can be pin reset / soft reset / power on reset. CD can be used to initialize the multi-byte input RGB format to/from on-chip SRAM mapping. Table 3: Host interfaces Summary PARALLEL INTERFACE The timing relationship between UC1682 internal control signal RD, WR and their associated bus actions are shown in the figure below. The Display RAM read interface is implemented as a two-stage pipe-line. This architecture requires that, every time memory address is modified, either in 8-bit mode or 4-bit mode, by either Set CA, or Set RA command, a dummy read cycle needs to be performed before the actual data can propagate through the pipe-line and be read from data port D[7:0]. There is no pipeline in write interface of Display RAM. Data is transferred directly from bus buffer to internal RAM on the rising edges of write pulses. 8-BIT & 4-BIT BUS OPERATION UC1682 supports both 8-bit and 4-bit bus width. The bus width is determined by pin BM[1]. 4-bit bus operation exactly doubles the clock cycles of 8-bit bus operation, MSB followed by LSB, including the dummy read, which also requires two clock cycles. The bus cycle of 4-bit mode is reset each time CD pin changes state (when CS is active). Revision 0.6 35 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 External CD ___ WR __ RD D[7:0] LLSB DL DL+K CMSB CLSB Dummy DC DC+1 MMSB MLSB Internal Write Read Data Latch Column Address L DL L+K DL+K L+K+1 Dummy C DC C+1 DC+1 C+2 DC+2 C+3 M FIGURE 6: 8 bit Parallel Interface & Related Internal Signals SERIAL INTERFACE UC1682 supports three serial modes, one 4-wire SPI mode (S8), one compact 3/4-wire mode (S8uc) and one 3-wire SPI mode (S9). Bus interface mode is determined by the wiring of the BM[1:0] and D[7:6]. See table in last page for more detail. content of the data been transferred. During each write cycle, 8 bits of data, MSB first, are latched on eight rising SCK edges into an 8-bit data holder. If CD=0, the data byte will be decoded as command. If CD=1, this 8-bit will be treated as data and transferred to proper address in the Display Data RAM on the rising edge of the last SCK pulse. Pin CD is examined when SCK is pulled low for the LSB (D0) of each token. S8 (4-WIRE) INTERFACE Only write operations are supported in 4-wire serial mode. Pin CS[1:0] are used for chip select and bus cycle reset. Pin CD is used to determine the CS0 SDA SCK CD D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 FIGURE 7.a: 4-wire Serial Interface (S8) CS0 SDA SCK CD D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 FIGURE 7.b: 3/4-wire Serial Interface (S8uc) 36 ES Specifications UC1682 80x104RGB CSTN Controller-Driver S8UC (3/4-WIRE) INTERFACE Only write operations are supported in this 3/4-wire serial mode. The data format is identical to S8. However, in addition to CS pins, CD pin transitions will also reset the bus cycle in this mode. So, if CS pins are hardwired to enable chip-select, the bus can work properly with only three signal pins. bit is CD, which determines the content of the following 8 bits of data, MSB first. These 8 command or data bits are latched on rising SCK edges into an 8-bit data holder. If CD=0, the data byte will be decoded as command. If CD=1, this 8bit will be treated as data and transferred to proper address in the Display Data RAM at the rising edge of the last SCK pulse. By sending CD information explicitly in the bit stream, control pin CD is not used, and should be connected to either VDD or VSS. The toggle of CS0 or CS1 for each byte of data/command is recommended but optional. S9 (3-WIRE) INTERFACE Only write operations are supported in this 3-wire serial mode. Pin CS[1-0] are used for chip select and bus cycle reset. On each write cycle, the first CS0 SDA SCK CD D7 D6 D5 D4 D3 D2 D1 D0 CD D7 D6 FIGURE 7.c: 3-wire Serial Interface (S9) Revision 0.6 37 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 HOST INTERFACE REFERENCE CIRCUIT VDD VCC D7-D0 CD WR RD D7-D0 CD WR0(WR) WR1(RD) VDD MPU ADDRESS IORQ DECODER VDD CS0 CS1 UC1682 RST ID VDD BM1 BM0 GND VSS FIGURE 8: 8080/8bit parallel mode reference circuit VDD VCC D7 D3-D0 CD WR RD D3-D0 CD WR0(WR) WR1(RD) VDD MPU ADDRESS IORQ DECODER VDD CS0 CS1 UC1682 RST ID BM1 BM0 GND VSS FIGURE 9: 8080/4bit parallel mode reference circuit 38 ES Specifications UC1682 80x104RGB CSTN Controller-Driver VDD VCC D7-D0 CD R/W E D7-D0 CD WR0(R/W) WR1(E) VDD MPU ADDRESS IORQ DECODER VDD CS0 CS1 UC1682 RST ID VDD BM1 BM0 GND VSS FIGURE 10: 6800/8bit parallel mode reference circuit VDD VCC D7 D3-D0 CD R/W E D3-D0 CD WR0(R/W) WR1(E) VDD MPU ADDRESS IORQ DECODER VDD VDD CS0 CS1 UC1682 RST ID BM1 BM0 GND VSS FIGURE 11: 6800/4bit parallel mode reference circuit Revision 0.6 39 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 VDD VCC SCK SDA CD D7 D6 SCK(D0) SDA(D3) CD WR0 WR1 VDD MPU ADDRESS IORQ DECODER VDD CS0 CS1 UC1682 RST ID BM1 BM0 GND VSS FIGURE 12: 4-Wires SPI (S8) serial mode reference circuit VDD VCC SCK SDA CD VDD D7 D6 SCK(D0) SDA(D3) CD WR0 WR1 CS0 VDD MPU VDD RST ID CS1 UC1682 BM1 BM0 GND VSS FIGURE 13: 3/4-Wires SPI (S8uc) serial mode reference circuit 40 ES Specifications UC1682 80x104RGB CSTN Controller-Driver VDD VCC SCK SDA VDD D7 SCK(D0) SDA(D3) WR0 WR1 VDD MPU ADDRESS IORQ DECODER VDD CS0 CS1 UC1682 RST ID VDD BM1 BM0 GND VSS FIGURE 14: 3-Wires SPI (S9) serial mode reference circuit Note * * ID pin is for production control. The connection will affect the content of D[7] when using Get Status command. Connect to VDD for "H" or VSS for "L". RST pin is optional. When RST pin is not used, connect the pin to VDD. Revision 0.6 41 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 DISPLAY DATA RAM DATA ORGANIZATION The input display data (depend on color mode) are stored to a dual port static RAM (RAM, for Display Data RAM) organized as 80x104X12. After setting CA and RA, the subsequent data write cycles will store the data for the specified pixel to the proper memory location. Please refer to the map in the following page between the relation of COM, SEG, SRAM, and various memory control registers. zero value is equivalent to scrolling the LCD display up or down (depends on MY) by SL rows. RAM ADDRESS GENERATION The mapping of the data stored in the display SRAM and the scanning COM electrodes can be obtained by combining the fixed COM scanning sequence and the following RAM address generation formula. When FL=0, during the display operation, the RAM line address generation can be mathematically represented as following: For the 1st line period of each field Line = SL Otherwise Line = Mod(Line+1, 80) Where Mod is the modular operator, and Line is the bit slice line address of RAM to be outputted to SEG drivers. Line 0 corresponds to the first bitslice of data in RAM. The above Line generation formula produces the "loop around" effect as it effectively resets Line to 0 when Line+1 reaches 80. Effects such as scrolling can be emulated by changing SL dynamically. DISPLAY DATA RAM ACCESS The Display RAM is a special purpose dual port RAM which allows asynchronous access to both its column and row data. Thus, RAM can be independently accessed both for Host Interface and for display operations. DISPLAY DATA RAM ADDRESSING A Host Interface (HI) memory access operation starts with specifying Row Address (RA) and Column Address (CA) by issuing Set Row Address and Set Column Address commands. If wrap-around (WA, AC[0]) is OFF (0), CA will stop incrementing after reaching the end of row (103), and system programmers need to set the values of RA and CA explicitly. If WA is ON (1), when CA reaches the end of a row, CA will be reset to 0 and RA will increment or decrement, depending on the setting of row Increment Direction (RID, AC[2]). When RA reaches the boundary of RAM (i.e. RA = 0 or 79), RA will be wrapped around to the other end of RAM and continue. MY IMPLEMENTATION Row Mirroring (MY) is implemented by reversing the mapping order between COM electrodes and RAM, i.e. the mathematical address generation formula becomes: For the 1 line period of each field Line = Mod(SL + MUX-1, 80) where MUX = CEN + 1 Otherwise Line = Mod(Line-1 , 80) Visually, the effect of MY is equivalent to flipping the display upside down. The data stored in display RAM are not affected by MY. st MX IMPLEMENTATION Column Mirroring (MX) is implemented by selecting either (CA) or (103-CA) as the RAM column address. Changing MX affects the data written to the RAM. Since MX has no effect on the data already stored in RAM, changing MX does not have immediate effect on the displayed pattern. To refresh the display, refresh the data stored in RAM after setting MX. ROW MAPPING COM electrode scanning orders are not affected by Start Line (SL), Fixed Line (FL) or Mirror Y (MY, LC[3]). Visually, register SL having a non- 42 ES Specifications UC1682 80x104RGB CSTN Controller-Driver WINDOW PROGRAM Window program is designed for data write in a specified window range of SRAM address. The procedure should start with window boundary registers setting (WPP0, WPP1, WPC0 and WPC1) and then enable AC[4]. After AC[4] sets, data can be written to SRAM within the window address range which is specified by (WPP0, WPC0) and (WPP1, WPC1). AC[4] should be cleared after any modification of window boundary registers and then set again in order to initialize another window program. The data write direction will be determined by AC[2:0] and MX settings. When AC[0]=1, the data write can be consecutive within the range of the specified window. AC[1] will control the data write in either column or row direction. AC[2] will result the data write starting either from row WPP0 or WPP1. MX is for the initial column address either from WPC0 to WPC1 or from (MCWPC0 to MC-WPC1). Example1: AC[2:0] = 001 MX=0 column 0 (WPP0, WPC0) Example 2: AC[2:0] = 111 MX = 0 103 (WPP0, WPC0) row 79 (WPP1,WPC1) (WPP1,WPC1) Revision 0.6 43 ULTRACHIP High-Voltage Mixed-Signal IC Row Adderss 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH RAM MY=0 SL=0 SL=16 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 (c) 1999 ~ 2003 MY=1 SL=0 SL=16 COM80 COM79 COM78 COM77 COM76 COM75 COM74 COM73 COM72 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM80 COM79 COM78 COM77 COM76 COM75 COM74 COM73 COM72 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH SEG308 SEG309 SEG310 SEG311 SEG312 COM76 COM77 COM78 COM79 COM80 COM60 COM61 COM62 COM63 COM64 COM5 COM4 COM3 COM2 COM1 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 SEG1 SEG2 SEG3 SEG4 SEG309 MX SEG312 SEG311 SEG310 SEG308 SEG5 0 SEG5 SEG4 SEG3 SEG2 Example for memory mapping: let MX = 0, MY = 0, SL = 0, LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 56K color ), according to the data shown in the above table (R: 11111b, G: 111111b, B: 11111b): 1st Byte write data: 11111111b 2nd Byte write data: 11111111b 44 SEG1 1 ES Specifications UC1682 80x104RGB CSTN Controller-Driver RESET & POWER MANAGEMENT TYPES OF RESET UC1682 has two different types of Reset: Power-ON-Reset and System-Reset. CHANGING OPERATION MODE In addition to Power-ON-Reset, two commands will initiate OM transitions: Power-ON-Reset is performed right after VDD is connected to power. Power-On-Reset will first wait for about 5~10mS, depending on the time required for VDD to stabilize, and then trigger the System Reset. System Reset can also be activated by software command or by connecting RST pin to ground. In the following discussions, Reset means System Reset. Set Display Enable, and System Reset. When DC[2] is modified by Set Display Enable, OM will be updated automatically. There is no other action required to enter Sleep mode. For maximum energy utilization, Sleep mode is designed to retain charges stored in external capacitors CB0, CB1, and CL. To drain these capacitors, use Reset command to activate the onchip draining circuit. RESET STATUS When UC1682 enters RESET sequence: Action Set Driver Enable to "0" Set Driver Enable to "1" Reset command or RST_ pin pulled "L" Power ON Reset Mode Sleep Normal Reset OM 10 11 00 * * Operation mode will be "Reset" System Status bits RS and BZ will stay as "1" until the Reset process is completed. When RS=1, the IC will only respond to Read Status command. All other commands are ignored. All control registers are reset to default values. Refer to Control Registers for details of their default values. Table 5: OM changes Even though UC1682 consumes very little energy in Sleep mode (typically 5uA or less); however, since all capacitors are still charged, the leakage through COM drivers may damage the LCD over the long term. It is therefore recommended to use Sleep mode only for brief Display OFF operations, such as full-frame screen updates, and to use RESET for extended screen OFF operations. * OPERATION MODES UC1682 has three operating modes (OM): Reset, Normal, Sleep. Mode OM Host Interface Clock LCD Drivers Charge Pump Draining Circuit Reset 00 Active OFF OFF OFF ON Sleep Normal 10 Active OFF OFF OFF OFF 11 Active ON ON ON OFF EXITING SLEEP MODE UC1682 contains internal logic to check whether VLCD and VBIAS are ready before releasing COM and SEG drivers from their idle states. When exiting Sleep or Reset mode, COM and SEG drivers will not be activated until UC1682 internal voltage sources are restored to their proper values. Table 4: Operating Modes Revision 0.6 45 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 POWER-UP SEQUENCE UC1682 power-up sequence is simplified by built-in "Power Ready" flags and the automatic invocation of System-Reset command after Power-ON-Reset. System programmers are only required to wait 5~ 10 ms before the CPU starting to issue commands to UC1682. No additional time sequences are required between enabling the charge pump, turning on the display drivers, writing to RAM or any other commands. However, while turning on VDD, VDD2/3 should be started not later than VDD. Delay allowance between VDD and VDD2/3 is illustrated as Figure 15-1. POWER-DOWN SEQUENCE To prevent the charge stored in capacitors CBX+, CBX-, and CL from damaging the LCD, when VDD is switched off, use Reset mode to enable the built-in draining circuit and discharge these capacitors. The draining resistor is 1K for both VLCD and VB+. It is recommended to wait 3 x RC for VLCD and 1.5 x RC for VB+. For example, if CL is 15nF, then the draining time required for VLCD is 0.5~1mS. When internal VLCD is not used, UC1682 will NOT drain VLCD during RESET. System designers need to make sure external VLCD source is properly drained off before turning off VDD. Turn on VDD Reset command Wait 5~10 mS Set OTPC[4] ( Ignore OTP value when "L" ) Wait ~1 mS Set LCD Bias Ratio (BR) Set Potential Meter (PM) Turn off VDD Set Display Enable Figure 16: Reference Power-Down Sequence Figure 15: Reference Power-Up Sequence TDelay > 0 s VDD2/3 > 2.4V VDD TWait > 50 mS > 1.8V VDD2/3 > VDD Tf < 10 mS T1 T2 10S < T1, T2 < 10 mS Figure 15-1: Delay allowance and Power Off-On Sequence 46 ES Specifications UC1682 80x104RGB CSTN Controller-Driver SAMPLE POWER MANAGEMENT COMMAND SEQUENCES The following tables are examples of command sequence for power-up, power-down and display ON/OFF operations. These are only to demonstrate some "typical, generic" scenarios. Designers are encouraged to study related sections of the datasheet and find out what the best parameters and control sequences are for their specific design needs. C/D W/R Type The type of the interface cycle. It can be either Command (0) or Data (1) The direction of dataflow of the cycle. It can be either Write (0) or Read (1). Required: Customer: Advanced: Optional: These items are required These items are not necessary if customer parameters are the same as default We recommend new users to skip these commands and use default values. These commands depend on what users want to do. POWER-UP Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R R - 0 0 0 0 0 0 0 0 0 1 . . 1 0 - 0 0 0 0 0 0 0 0 0 0 . . 0 0 - 1 0 0 1 1 1 1 1 # # . . # 1 - 0 0 0 1 0 1 1 0 # # . . # 0 - 1 0 1 0 1 0 1 0 # # . . # 1 - 1 0 0 0 0 1 0 0 # # . . # 0 - 1 0 0 0 0 0 1 0 # # . . # 1 - 0 0 1 # 0 1 0 0 # # . . # 1 - 0 0 # # # # # 0 # # . . # 1 Chip action Comments Wait 5~10ms after VDD is ON Ignore OTP value Set up LCD format specific parameters, MX, MY, etc. Fine tune for power, flicker, contrast, and shading. LCD specific operating voltage setting C C A C C R O R - Automatic Power-ON Reset. 0 (37) Set OTP operation 0 Control. (Double-type Command) # (5) Set Temp. Compensation # (20) Set LCD Mapping # (15) Set Line Rate # (22) Set Color Mode # (26) Set LCD Bias Ratio 1 (11) Set VBIAS Potentiometer # # . Write display RAM . # 1 (18) Set Display Enable Set up display image POWER-DOWN Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R R 0 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 1 - Chip action Comments Wait ~1ms before VDD OFF 0 (23) System Reset - Draining capacitor BRIEF DISPLAY-OFF Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R C Chip action Comments 0 0 1 0 1 0 1 1 1 0 (18) Set Display Disable 1 0 # # # # # # # # Write display RAM Set up display image (Image update is optional. Data in . . ........ the RAM is retained through . . ........ the SLEEP state.) 1 0 ######## R 0 0 1 0 1 0 1 1 1 1 (18) Set Display Enable * This is only recommended for very brief display OFF (under 10mS). If image becomes unstable use the Extended Display OFF approach shown below. Revision 0.6 47 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 EXTENDED DISPLAY-OFF Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R - - R C 0 - - 0 - - 1 - - 1 - - 1 - - 0 - - 0 - - 0 - - 1 - - - - Repeat power-up sequence Chip action Comments CB1, CB1, CLCD discharged. Extended display OFF Zzzz... System waking up Repeat power up register setting sequence Set up display image (Image update is optional. Data in the RAM is retained through the RESET state.) 0 (23) System Reset. ######## 0 1 ........ . . Write display RAM ........ . . ######## 0 1 R 0 0 1 0 1 0 1 1 1 1 (18) Set Display Enable * The sequence is basically the same as the power up sequence, except Power-ON Reset is replaced by System Reset command, and an extended idle time in between. 48 ES Specifications UC1682 80x104RGB CSTN Controller-Driver ABSOLUTE MAXIMUM RATINGS In accordance with IEC134, note 1, 2 and 3. Symbol VDD VDD2 VDD3 VLCD VIN TOPR TSTR Logic Supply voltage Parameter LCD Generator Supply voltage Analog Circuit Supply voltage LCD Driving voltage (-25 C ~ +75 C) Digital input signal Operating temperature range Storage temperature O O Min. -0.3 -0.3 -0.3 -0.3 -0.4 -30 -55 Max. +4.0 +4.0 +4.0 +12.0 VDD + 0.5 +85 +125 Unit V V V V V o o C C Notes 1. 2. VDD based on VSS = 0V Stress beyond ranges listed above may cause permanent damages to the device. Revision 0.6 49 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 SPECIFICATIONS DC CHARACTERISTICS Symbol VDD VDD2/3 VLCD VD VIL VIH VOL VOH IIL CIN COUT R0(SEG) R0(COM) Parameter Supply for digital circuit Supply for bias & pump Charge pump output LCD data voltage Input logic LOW Input logic HIGH Output logic LOW Output logic HIGH Input leakage current Input capacitance Output capacitance SEG output impedance COM output impedance Average Line rate VDD2/3 VDD2/3 Conditions Min. 1.8 2.4 Typ. Max. 3.3 3.3 Unit V V V V V V V V 2.4V, 25 C 2.4V, 25OC 0.9 0.8VDD O 9.9 10.5 1.5 0.2VDD 0.2VDD 0.8VDD 1.5 5 5 VLCD = 9.9V VLCD = 9.9V LC[4:3] = 11b 18.4 1.5 2.0 20 10 10 3.0 4.0 22.4 A pF pF k K Klps fLINE Note: When VDD < 2.0, letting VIL = 0 and VIH = VDD is recommended. POWER CONSUMPTION VDD = 2.8V, Bias Ratio = 8, PM = 142, VLCD = 9.9V, Line Rate =10b, PL = 11b, MR =80, Bus mode =6800, CL = 5nF~50nF, CB = 2F. All SEG/COM outputs are open-circuit. Display Pattern All-OFF 2-pixel checker VLCD Conditions Bus = idle Bus = idle Bus = idle (standby current) Typ. (A) 665 860 - Max. (A) 2000 2000 5 50 ES Specifications UC1682 80x104RGB CSTN Controller-Driver AC CHARACTERISTICS CD CS0 CS1 tAS80 tCSSA80 WR0 WR1 Write D[7:0] tACC80 Read D[7:0] tOD80 tCY80 tPWR80, tPWW80 tHPW80 tAH80 tCSH80 tCSSD80 tDS80 tDH80 FIGURE 17: Parallel Bus Timing Characteristics (for 8080 MCU) (2.5V VDD< 3.3V, Ta= -30 to +85 C) o Symbol tAS80 tAH80 tCY80 Signal CD Description Address setup time Address hold time System cycle time 8 bits bus (read) (write) 4 bits bus (read) (write) Pulse width 8 bits (read) 4 bits Pulse width 8 bits (write) 4 bits High pulse width 8 bits bus (read) (write) 4 bits bus (read) (write) Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 0 15 140 80 140 80 70 70 40 40 70 40 70 40 30 15 - 25 10 10 20 Max. - - Units ns ns tPWR80 tPWW80 tHPW80 WR1 WR0 WR0, WR1 - - - ns ns ns tDS80 tDH80 tACC80 tOD80 tCSSA80 tCSSD80 tCSH80 D0~D7 - 80 40 ns ns ns CL = 100pF CS1/CS0 Revision 0.6 51 ULTRACHIP High-Voltage Mixed-Signal IC o (c) 1999 ~ 2003 (1.8V VDD< 2.5V, Ta= -30 to +85 C) Symbol tAS80 tAH80 tCY80 Signal CD Description Address setup time Address hold time System cycle time 8 bits bus (read) (write) 4 bits bus (read) (write) Pulse width 8 bits (read) 4 bits (read) Pulse width 8 bits (write) 4 bits (write) High pulse width 8 bits bus (read) (write) 4 bits bus (read) (write) Data setup time Data hold time Read access time Output disable time Condition Min. 0 30 280 160 280 160 140 140 80 80 140 80 140 80 60 30 50 20 20 40 Max. - - Units ns ns tPWR80 tPWW80 tHPW80 WR1 WR0 - - - ns ns ns WR0, WR1 tDS80 tDH80 tACC80 tOD80 tCSSA80 tCSSD80 tCSH80 D0~D7 - 160 80 ns ns ns CL = 100pF CS1/CS0 Chip select setup time 52 ES Specifications UC1682 80x104RGB CSTN Controller-Driver CD CS0 CS1 tAS68 tCSSA68 tCY68 tPWR68, tPWW68 WR1 tDS68 Write D[7:0] tACC68 Read D[7:0] tOD68 tDH68 tLPW68 tAH68 tCSH68 tCSSD68 FIGURE 18: Parallel Bus Timing Characteristics (for 6800 MCU) (2.5V VDD< 3.3V, Ta= -30 to +85 C) o Symbol tAS68 tAH68 TCY68 Signal CD Description Address setup time Address hold time System cycle time 8 bits bus (read) (write) 4 bits bus (read) (write) Pulse width 8 bits (read) 4 bits Pulse width 8 bits (write) 4 bits Low pulse width 8 bits bus (read) (write) 4 bits bus (read) (write) Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 0 20 140 80 140 80 70 70 40 40 70 40 70 40 30 15 - 25 10 10 20 Max. - - Units ns ns tPWR68 tPWW68 tLPW68 WR1 - - - ns ns ns tDS68 tDH68 tACC68 tOD68 tCSSA68 tCSSD68 tCSH68 D0~D7 - 80 40 ns ns ns CL = 100pF CS1/CS0 Revision 0.6 53 ULTRACHIP High-Voltage Mixed-Signal IC o (c) 1999 ~ 2003 (1.8V VDD< 2.5V, Ta= -30 to +85 C) Symbol tAS68 tAH68 TCY68 Signal CD Description Address setup time Address hold time System cycle time 8 bits bus (read) (write) 4 bits bus (read) (write) Pulse width 8 bits (read) 4 bits Pulse width 8 bits (write) 4 bits Low pulse width 8 bits bus (read) (write) 4 bits bus (read) (write) Data setup time Data hold time Read access time Output disable time Condition Min. 0 40 280 160 280 160 140 140 80 80 140 80 140 80 60 30 50 20 20 40 Max. - - Units ns ns tPWR68 tPWW68 tLPW68 WR1 - - - ns ns ns tDS68 tDH68 tACC68 tOD68 TCSSA68 TCSSD68 TCSH68 D0~D7 - 160 80 ns ns ns CL = 100pF CS1/CS0 Chip select setup time 54 ES Specifications UC1682 80x104RGB CSTN Controller-Driver CD CS0 CS1 tASS8 tCSSAS8 tCYS8 tLPWS8 SCK tDSS8 SDA tDHS8 tHPWS8 tAHS8 tCSHS8 tCSSDS8 FIGURE 19: Serial Bus Timing Characteristics (for S8) o (2.5V VDD< 3.3V, Ta= -30 to +85 C) Symbol tASS8 tAHS8 tCYS8 tLPWS8 tHPWS8 tDSS8 tDHS8 tCSSAS8 tCSSDS8 tCSHS8 Signal CD Description Address setup time Address hold time System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 0 15 80 35 35 30 20 10 10 20 Max. - - - - - - Units ns ns ns ns ns ns ns SCK SDA CS1/CS0 (1.8V VDD< 2.5V, Ta= -30 to +85 C) o Symbol tASS8 tAHS8 tCYS8 tLPWS8 tHPWS8 tDSS8 tDHS8 tCSSAS8 tCSSDS8 tCSHS8 Signal CD Description Address setup time Address hold time System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 0 30 160 70 70 60 40 20 20 40 Max. - - - - - - Units ns ns ns ns ns ns ns SCK SDA CS1/CS0 Revision 0.6 55 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 CS0 CS1 tCSS9 tCYS9 tWLS9 SCK tDSS9 SDA tDHS9 tWHS9 tCSHS9 tCSSDS9 FIGURE 20: Serial Bus Timing Characteristics (for S9) o (2.5V VDD< 3.3V, Ta= -30 to +85 C) Symbol tCYS9 tLPWS9 tHPWS9 tDSS9 tDHS9 tCSSAS9 tCSSDS9 tCSHS9 Signal SCK Description System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 80 35 35 30 20 10 10 20 Max. - - - - Units ns ns ns ns ns SDA CS1/CS0 (1.8V VDD< 2.5V, Ta= -30 to +85 C) o Symbol tCYS9 tLPWS9 tHPWS9 tDSS9 tDHS9 tCSSAS9 tCSSDS9 tCSHS9 Signal SCK Description System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 160 70 70 60 40 20 20 40 Max. - - - - Units ns ns ns ns ns SDA CS1/CS0 56 ES Specifications UC1682 80x104RGB CSTN Controller-Driver tRW RST FIGURE 21: Reset Characteristics o (1.8V VDD< 3.3V, Ta= -30 to +85 C) Symbol tRW Signal RST Description Reset low pulse width Condition Min. 500 Max. - Units S Revision 0.6 57 ULTRACHIP High-Voltage Mixed-Signal IC (c) 1999 ~ 2003 PHYSICAL DIMENSIONS PAD COORDINATES DIE SIZE: 13.944mm x 1.494mm DIE THICKNESS: 0.5mm BUMP HEIGHT: 17m 1m (within die) MINIMUM BUMP PITCH: SEG: 41.5m (Typ.) COM: 50.0m (Typ.) MINIMUM BUMP GAP: 17m (Typ.) COORDINATE ORIGIN: Chip center PAD REFERENCE: Pad center (Drawing and coordinates are for the Circuit/Bump view.) 58 ES Specifications UC1682 80x104RGB CSTN Controller-Driver ALIGNMENT MARK INFORMATION U-Left Mark U-Right Mark (0,0) D-Left Mark SHAPE OF THE ALIGNMENT MARK: 1 2 3 2 3 1 3 1 C 2 4 D-Right Mark NOTE: Alignment mark is on Metal3 under Passivation. COORDINATES: U-Left Mark X 1 2 3 Y X U-Right Mark Y -6887.1 -6879.1 -6846.2 615.7 606.5 598.5 6853.2 6882.4 6858.1 608.5 589.2 613.4 D-Left Mark X 1 2 3 4 C Y X D-Right Mark Y -5690.3 -5678.3 -5701.8 -5666.8 -5684.3 -612.1 -667.2 -633.7 -645.7 -639.7 5535.4 5547.4 5523.9 5558.9 5541.4 -612.1 -667.2 -633.7 -645.7 -639.7 TOP METAL AND PASSIVATION: SiN / 7KA SiO2 / 5KA Metal3 / 9KA SiON / (TBD)KA Metal3 / 9KA FOR NON-OTP PROCESS CROSS-SECTION FOR OTP PROCESS CROSS-SECTION Revision 0.6 59 ULTRACHIP High-Voltage Mixed-Signal IC (c)1999~2003 PI INFORMATION PI THICKNESS: 3.6 0.4 m MINIMUM SEPARATION OF BUMP TO EDGE OF POLYIMIDE LAYER: 20 m 60 ES Specifications UC1682 80x104RGB CSTN Controller-Driver PAD COORDINATES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 # Pad Name DUMMY COM2 COM4 COM6 COM8 COM10 COM12 COM14 COM16 COM18 COM20 COM22 COM24 COM26 COM28 COM30 COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 COM48 DUMMY COM50 COM52 COM54 COM56 COM58 COM60 COM62 COM64 COM66 COM68 COM70 COM72 COM74 COM76 COM78 COM80 D7 VDDX D6 D5 D4 D3 D2 D1 D0 VBIAS RST_ CS1 VDDX CS0 CD WR0 VDDX WR1 -6867.9 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.4 -6867.9 -6479.6 -6429.6 -6379.6 -6329.6 -6279.6 -6229.6 -6179.6 -6129.6 -6079.6 -6029.6 -5979.6 -5929.6 -5879.6 -5829.6 -5779.6 -5729.6 -5481.6 -5402.3 -5323.8 -5093.8 -4863.8 -4633.8 -4403.8 -4173.8 -3943.8 -3706.0 -3501.3 -3407.5 -3333.2 -3256.9 -3173.6 -3086.1 -3009.0 -2930.4 X 649.7 570.3 520.3 470.3 420.3 370.3 320.3 270.3 220.3 170.3 120.3 70.3 20.3 -29.8 -79.8 -129.8 -179.8 -229.8 -279.8 -329.8 -379.8 -429.8 -479.8 -529.8 -579.8 -654.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 Y 85 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 85 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 W 50 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 50 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 H 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 # Pad Name BM0 VDDX BM1 TST4 TST4 TP5 TST2 TP4 TP3 TP2 TP1 ID VSS VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VDD3 VDD3 VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD VDD VDD VDD VDD VDD VB0+ VB0+ VB0+ VB0+ VB0+ VB0+ VB0+ VB0+ VB0+ SB0+ VB1+ VB1+ VB1+ VB1+ VB1+ VB1+ VB1+ VB1+ VB1+ SB1+ VB1VB1- -2840.0 -2760.8 -2681.9 -2593.9 -2523.9 -2195.0 -2124.8 -1800.8 -1727.1 -1657.1 -1587.1 -1480.7 -1391.6 -1311.6 -1231.6 -1151.6 -1071.6 -991.5 -911.5 -831.5 -751.5 -671.5 -591.5 -511.5 -431.5 -351.5 -275.1 -97.5 -17.5 62.5 141.1 219.5 493.0 573.0 653.0 733.0 813.0 893.0 972.9 1042.9 1112.9 1182.9 1252.9 1475.7 1546.0 1616.0 1686.0 1756.0 1974.9 2044.9 2114.9 2184.9 2254.9 2477.7 2548.0 2618.0 2688.0 2758.0 2976.9 3046.9 X -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 Y 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 W 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 H Revision 0.6 61 ULTRACHIP High-Voltage Mixed-Signal IC (c)1999~2003 Y W H # Pad Name X Y W H 121 VB1122 VB1123 VB1124 VB1125 VB1126 VB1127 VB1128 SB1129 VB0130 VB0131 VB0132 VB0133 VB0134 VB0135 VB0136 VB0137 VB0138 SB0139 VLCDIN 140 VLCDIN 141 VLCDOUT 142 VLCDOUT 143 COM79 144 COM77 145 COM75 146 COM73 147 COM71 148 COM69 149 COM67 150 COM65 151 COM63 152 COM61 153 COM59 154 COM57 155 COM55 156 COM53 157 COM51 158 COM49 159 DUMMY 160 COM47 161 COM45 162 COM43 163 COM41 164 COM39 165 COM37 166 COM35 167 COM33 168 COM31 169 COM29 170 COM27 171 COM25 172 COM23 173 COM21 174 COM19 175 COM17 176 COM15 177 COM13 178 COM11 179 COM9 180 COM7 181 COM5 182 COM3 183 COM1 # Pad Name 3116.9 3186.9 3256.9 3479.7 3550.0 3620.0 3690.0 3760.0 3978.9 4048.9 4118.9 4188.9 4258.9 4481.7 4552.0 4622.0 4692.0 4762.0 5118.4 5188.7 5258.7 5328.7 5610.6 5660.6 5710.6 5760.6 5810.6 5860.6 5910.6 5960.6 6010.6 6060.6 6110.6 6160.6 6210.6 6260.6 6310.6 6360.6 6868.1 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 6867.6 X -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -645.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -642.4 -658.7 -594.9 -544.9 -494.9 -444.9 -394.9 -344.9 -294.9 -244.9 -194.9 -144.9 -94.9 -44.9 5.1 55.1 105.1 155.1 205.1 255.1 305.1 355.1 405.1 455.1 505.1 555.1 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 85 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 50 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 DUMMY SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 6868.1 6538.0 6496.5 6455.0 6413.5 6372.0 6330.5 6289.0 6247.5 6206.0 6164.5 6123.0 6081.5 6040.0 5998.5 5957.0 5915.5 5874.0 5832.5 5791.0 5749.5 5708.0 5666.5 5625.0 5583.5 5542.0 5500.5 5459.0 5417.5 5376.0 5334.5 5293.0 5251.5 5210.0 5168.5 5127.0 5085.5 5044.0 5002.5 4961.0 4919.5 4878.0 4836.5 4795.0 4753.5 4712.0 4670.5 4629.0 4587.5 4546.0 4504.5 4463.0 4421.5 4380.0 4338.5 4297.0 4255.5 4214.0 4172.5 4131.0 4089.5 3962.3 3920.8 649.7 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 85 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 50 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 62 ES Specifications UC1682 80x104RGB CSTN Controller-Driver 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 # Pad Name SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 3879.3 3837.8 3796.3 3754.8 3713.3 3671.8 3630.3 3588.8 3547.3 3505.8 3464.3 3422.8 3381.3 3339.8 3298.3 3256.8 3215.3 3173.8 3132.3 3090.8 3049.3 3007.8 2966.3 2924.8 2883.3 2841.8 2800.3 2758.8 2717.3 2675.8 2634.3 2592.8 2551.3 2509.8 2468.3 2426.8 2385.3 2343.8 2302.3 2260.8 2219.3 2177.8 2136.3 2094.8 2053.3 2011.8 1970.3 1928.8 1887.3 1845.8 1804.3 1762.8 1721.3 1679.8 1638.3 1596.8 1555.3 1513.8 1472.3 1430.8 1389.3 1347.8 1306.3 X 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 Y 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 W 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 H 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 # Pad Name SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 SEG161 SEG162 SEG163 SEG164 SEG165 SEG166 SEG167 SEG168 SEG169 SEG170 SEG171 SEG172 SEG173 SEG174 SEG175 SEG176 SEG177 SEG178 SEG179 SEG180 SEG181 SEG182 SEG183 SEG184 SEG185 SEG186 SEG187 SEG188 1264.8 1223.3 1181.8 1140.3 1098.8 1057.3 1015.8 974.3 932.8 891.3 849.8 808.3 766.8 725.3 683.8 642.3 600.8 559.3 517.8 476.3 434.8 393.3 351.8 310.3 268.8 227.3 185.8 144.3 102.8 61.3 19.8 -21.7 -63.2 -104.7 -146.2 -187.7 -229.2 -270.7 -312.2 -353.7 -395.2 -436.7 -478.2 -519.7 -561.2 -602.7 -644.2 -685.7 -727.2 -768.7 -810.2 -851.7 -893.2 -934.7 -976.2 -1017.7 -1059.2 -1100.7 -1142.2 -1183.7 -1225.2 -1266.7 -1308.2 X 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 Y 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 W 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 H Revision 0.6 63 ULTRACHIP High-Voltage Mixed-Signal IC (c)1999~2003 Y W H # Pad Name X Y W H 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 # Pad Name SEG189 SEG190 SEG191 SEG192 SEG193 SEG194 SEG195 SEG196 SEG197 SEG198 SEG199 SEG200 SEG201 SEG202 SEG203 SEG204 SEG205 SEG206 SEG207 SEG208 SEG209 SEG210 SEG211 SEG212 SEG213 SEG214 SEG215 SEG216 SEG217 SEG218 SEG219 SEG220 SEG221 SEG222 SEG223 SEG224 SEG225 SEG226 SEG227 SEG228 SEG229 SEG230 SEG231 SEG232 SEG233 SEG234 SEG235 SEG236 SEG237 SEG238 SEG239 SEG240 SEG241 SEG242 SEG243 SEG244 SEG245 SEG246 SEG247 SEG248 SEG249 SEG250 SEG251 -1349.7 -1391.2 -1432.7 -1474.2 -1515.7 -1557.2 -1598.7 -1640.2 -1681.7 -1723.2 -1764.7 -1806.2 -1847.7 -1889.2 -1930.7 -1972.2 -2013.7 -2055.2 -2096.7 -2138.2 -2179.7 -2221.2 -2262.7 -2304.2 -2345.7 -2387.2 -2428.7 -2470.2 -2511.7 -2553.2 -2594.7 -2636.2 -2677.7 -2719.2 -2760.7 -2802.2 -2843.7 -2885.2 -2926.7 -2968.2 -3009.7 -3051.2 -3092.7 -3134.2 -3175.7 -3217.2 -3258.7 -3300.2 -3341.7 -3383.2 -3424.7 -3466.2 -3507.7 -3549.2 -3590.7 -3632.2 -3673.7 -3715.2 -3756.7 -3798.2 -3839.7 -3881.2 -3922.7 X 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 SEG252 SEG253 SEG254 SEG255 SEG256 SEG257 SEG258 SEG259 SEG260 SEG261 SEG262 SEG263 SEG264 SEG265 SEG266 SEG267 SEG268 SEG269 SEG270 SEG271 SEG272 SEG273 SEG274 SEG275 SEG276 SEG277 SEG278 SEG279 SEG280 SEG281 SEG282 SEG283 SEG284 SEG285 SEG286 SEG287 SEG288 SEG289 SEG290 SEG291 SEG292 SEG293 SEG294 SEG295 SEG296 SEG297 SEG298 SEG299 SEG300 SEG301 SEG302 SEG303 SEG304 SEG305 SEG306 SEG307 SEG308 SEG309 SEG310 SEG311 SEG312 -3964.2 -4005.7 -4047.2 -4088.7 -4130.2 -4171.7 -4213.2 -4254.7 -4296.2 -4337.7 -4379.2 -4420.7 -4462.2 -4503.7 -4545.2 -4586.7 -4628.2 -4669.7 -4711.2 -4752.7 -4794.2 -4835.7 -4877.2 -4918.7 -4960.2 -5001.7 -5043.2 -5084.7 -5126.2 -5167.7 -5209.2 -5250.7 -5292.2 -5333.7 -5375.2 -5416.7 -5458.2 -5499.7 -5541.2 -5582.7 -5624.2 -5665.7 -5707.2 -5748.7 -5790.2 -5831.7 -5873.2 -5914.7 -5956.2 -5997.7 -6039.2 -6080.7 -6122.2 -6163.7 -6205.2 -6246.7 -6288.2 -6329.7 -6371.2 -6412.7 -6454.2 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 628.6 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 24.5 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 64 ES Specifications UC1682 80x104RGB CSTN Controller-Driver TRAY INFORMATION Unless Otherwise Specified Unit mm General N/A Roughness Tolerance see Dimension drawing detail ULTRA CHIP INC. 2" IC Tray Scale N/A Proj. Package Code Type:H20-558*68-28(30) Drawn By Angle N/A Date Iris Chen 10-21-02' Material Checked Approved Drawing No. Rev. Alvin Chang Alvin Chang A 10-21-02' 10-21-02' Sheet 1 of 1 Size A4 Revision 0.6 65 (c)1999~2003 4 METAL(Cu) 3 2 1 D D SOLDER RESIST 0.094 P0.094x41=3.854 (W=0.047) POLYIMIDE UNIT SHOWN FROM COPPER SIDE C L 28.782 (Cut line) 0.094 P0.062x313=19.406, W=0.031 27.968 (Alignment Mark) D P0.094x41=3.854 (W=0.047) C A 4.75 x 5 S.P. = 23.75 1.42(SQ) 2 1 398 4 21 C 4.5 (Alignment hole) 1 4.98 Max (Resin Area) 16.93 Max (Resin Area) 398 12.2 0.2 (S/R) 3 17 (Cut line) 7.733 (IC Center) IC C L B 8.VDD2,3 11.VBIAS 12.TST4 15.WR1 16.WR0 2.VLCD 13.BM1 14.BM0 20.RST 18.CS0 19.CS1 5.VB1+ 6.VB0+ 3.VBO4.VB17.VDD 21.DO 9.VSS 17.CD 29.NC 22.D1 23.D2 24.D3 25.D4 26.D5 27.D6 1.NC 28.D7 10.ID B B 0.5 1 14.391 (IC Center) P0.9x28=25.2 (W=0.45) 29 2 0.2 2.8 4 0.8 max. (Include IC) 26 (Alignment Hole) 26.65 (PI opening) 27.8 0.2 (S/R) 28.782 (Cut line) 31.82 34.98 0.17 High-Voltage Mixed-Signal IC COF INFORMATION ULTRACHIP A A U LTRA C HIP INC. Revise Describtion 5 4 3 2 1 New version 10/24/2002 Jack DATE DFTG CHK APPVL TITLE UC1682 COF Package Drawing A DRAWING NO. UC 1 6 8 2 4 3 2 FB REV 1 PROJECTION SCALE 1:1 SHT 1 of 2 1 66 ES Specifications 4 3 2 1 UC1682 80x104RGB CSTN Controller-Driver 0.74 Component List No. 1 2 3 2- 1.1(PI) D 0.8 0.407 Material Base Film Copper Solder Resist 4 Plating D C 0.1 0.8 0.1 2- 1.0 (Cu hole) C Output Input Detail "A" NC COM 79 COM 77 Detail "B" Reel 405 UN-Winding Direction SEG 306 SEG 307 SEG 308 SEG 309 SEG 310 SEG 311 SEG 312 NC COM 2 COM 4 COM 78 COM 80 NC Polyimide NC COM 3 COM 1 NC NC SEG 1 Copper After OLB 349 350 351 352 353 354 355 356 357 358 359 396 397 398 B B 40 41 42 43 44 1 2 3 Winding Direction B UC1682B IC NC VLCD VB0VB1VB1+ VB0+ VDD VDD2,3 ID VBIAS TST4 BM1 BM0 WR1 WR0 CD CS0 CS1 RST D0 D1 D2 D3 D4 D5 D6 D7 NC VSS UNIT SHOWN FROM COPPER SIDE Revise Describtion 5 4 3 2 1 New version DATE DFTG CHK APPVL TITLE UC1682 COF Package Drawing DRAWING NO. 10/24/2002 Jack UC 1 6 8 2 4 3 2 FB REV 1 PROJECTION SCALE 1:1 SHT 2 of 2 1 Revision 0.6 A U LTRA C HIP INC. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 A 67 ULTRACHIP High-Voltage Mixed-Signal IC (c)1999~2003 REVISION HISTORY Version 0.0 0.1 0.6 Contents Preliminary specification New release Figure 15 "Reference Power-Up Sequence" is updated for OTP. (Section "Reset & Power Management", page 46; "Power Up" table, page 47.) Date of Rev. Jul. 10, 2003 Jul. 24, 2003 Aug. 11, 2003 68 ES Specifications |
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